Trench FET having merged gate dielectric
View Patent ↗In one implementation, a trench field-effect transistor (trench FET) includes a semiconductor substrate having a drain region, a drift zone over the drain region, and depletion trenches formed over the drain region. Each depletion trench includes a depletion trench dielectric and a depletion electrode. The trench FET can further include a respective bordering gate trench situated alongside each depletion trench, each bordering gate trench having a gate electrode and a gate dielectric. The gate dielectric is merged with the depletion trench dielectric between the depletion electrode and the gate electrode.
1. A trench field-effect transistor (trench FET) comprising:
a semiconductor substrate including a drain region and a drift zone over said drain region;
a plurality of depletion trenches over said drain region, each of said plurality of depletion trenches having a depletion trench dielectric and a depletion electrode;
a respective bordering gate trench situated alongside each of said plurality of depletion trenches, each said bordering gate trench having a gate electrode and a gate dielectric;
said gate dielectric being merged with said depletion trench dielectric over said drift zone between said depletion electrode and said gate electrode.
2. The trench FET of claim 1 , wherein said gate dielectric is substantially thinner than said depletion trench dielectric.
3. The trench FET of claim 1 , wherein said respective bordering gate trench comprises only one bordering gate trench situated alongside each of said plurality of depletion trenches.
4. The trench FET of claim 1 , wherein said depletion electrode is electrically coupled to a source of said trench FET.
5. The trench FET of claim 1 , wherein said plurality of depletion trenches are at least one and a half times deeper than said respective bordering gate trench.
6. The trench FET of claim 1 , further comprising a channel layer including source regions formed over said drift zone.
7. The trench FET of claim 1 , wherein said drift zone comprises an epitaxial silicon layer.
8. The trench FET of claim 1 , wherein at least one of said gate dielectric and said depletion trench dielectric comprises silicon oxide.
9. The trench FET of claim 1 , wherein said gate dielectric comprises a high-κ dielectric.
10. The trench FET of claim 1 , wherein said trench FET is an n-channel FET.