SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

1 . A semiconductor device comprising:

a field effect transistor (FET) chip;

pads provided on an upper surface of the FET chip;

bumps provided on at least one of the pads;

leads that include first portions that are connected to the FET chip by the bumps and extend along the upper surface of the FET chip, and second portions that contact surfaces of the first portions along the upper surface of the FET chip and extend along a side surface of the FET chip, the leads being formed by press or cutting; and

a seal layer that seals the FET chip and the leads and a surface from which the second portions of the leads are exposed, the surface of the seal layer being on a lower surface side of the FET chip.

2 . The semiconductor device according to claim 1 , wherein the first portions of the leads have a thickness different in measurement from a width of the second portions.

3 . The semiconductor device according to claim 1 , wherein the second portion of one of the leads connected to a source pad that is one of the pads and the second portion of another one of the leads connected to a drain pad that is another one of the pads are exposed from the seal layer in positions between which the FET chip is interposed.

4 . The semiconductor device according to claim 1 , wherein the FET chip is a high electron mobility transistor chip.

5 . The semiconductor device according to claim 1 , wherein the FET chip is a high electron mobility transistor chip using a GaN-based semiconductor.

6 . The semiconductor device according to claim 1 , wherein the bumps provided on the at least one of the pads are arranged in rows and columns at equal intervals.

7 . The semiconductor device according to claim 1 , wherein the leads have third portions that contact opposite surfaces of the first portions to the surfaces of the first portions along the upper surface of the FET chip and extend a direction away from the opposite surfaces, and the third portions are exposed from the seal layer.

8 . The semiconductor device according to claim 7 , wherein the third portions contact surfaces of the first portions opposite to the surfaces of the first portions along the upper surface of the FET chip, and extends on an imaginary extension line of the second portion.

9 . The semiconductor device according to claim 7 , wherein the third portions have a width different in measurement from a thickness of the first portions.

10 . The semiconductor device according to claim 7 , further comprising protrusion electrodes provided on the third portions of the leads exposed from the seal layer.

11 . The semiconductor device according to claim 10 , wherein the protrusion electrodes have a height equal to or larger than 150 μm.

12 . The semiconductor device according to claim 7 , wherein the third portions of the leads exposed from the seal layer have a rectangular shape.

13 . The semiconductor device according to claim 7 , wherein the third portions of the leads exposed from the seal layer have a circular shape.

14 . A semiconductor device comprising first and second semiconductor devices each including:

a field effect transistor (FET) chip;

pads provided on an upper surface of the FET chip;

bumps provided on at least one of the pads;

leads that include first portions that are connected to the FET chip by the bumps and extend along the upper surface of the FET chip, and second portions that contact surfaces of the first portions along the upper surface of the FET chip and extend along a side surface of the FET chip; and

a seal layer that seals the FET chip and the leads and a surface from which the second portions of the leads are exposed, the surface of the seal layer being on a lower surface side of the FET chip,

the leads that include third portions that contact opposite surfaces of the first portions to the surfaces of the first portions along the upper surface of the FET chip and extend a direction away from the opposite surfaces, the third portions being exposed from the seal layer,

the first and second semiconductor devices that include a stacked structure in which the third portions of the leads of the first semiconductor device are connected to the second portions of the leads of the second semiconductor device.

15 . A method for fabricating a semiconductor device comprising:

preparing a metal plate that includes groove portions and bank portions arranged in a form of stripes;

forming cutout patterns that define leads extending from the groove portions to the bank portions in the metal plate by press or cutting;

connecting bumps provided on pads on an upper surface of each of field effect transistor (FET) chips to the groove portions of the leads defined by the cutout patterns, at least two bumps out of the bumps being provided on at least one of the pads,

dividing the metal plate into individual FET chips by cutting; and

forming a seal layer that seals the individual FET chips and the leads so that surfaces of the leads along lower surfaces of the individual FET chips are exposed.

16 . The method according to claim 15 , wherein:

the forming of the cutout patterns forms the cutout patterns arranged in rows and columns in the metal plate; and

the connecting of the bumps connects the bumps provided on the pads on the upper surfaces of the FET chips to the groove portions of the leads defined by the cutout patterns.

17 . The method according to claim 15 , wherein the preparing of the metal plate prepares the metal plate that includes protrusions that are provided on a surface of the metal plate opposite to another surface on which the groove portions and the bank portions are arranged and are aligned with sides of the bank portions.