Package with SoC and integrated memory
A semiconductor package includes a processor die (e.g., an SoC) and one or more memory die (e.g., DRAM) coupled to a ball grid array (BGA) substrate. The processor die and the memory die are coupled to opposite sides of the BGA substrate using terminals (e.g., solder balls). The package may be coupled to a printed circuit board (PCB) using one or more terminals positioned around the perimeter of the processor die. The PCB may include a recess with at least part of the processor die being positioned in the recess. Positioning at least part of the processor die in the recess reduces the overall height of the semiconductor package assembly. A voltage regulator may also be coupled to the BGA substrate on the same side as the processor die with at least part of the voltage regulator being positioned in the recess a few millimeters from the processor die.
1. A semiconductor device package assembly, comprising:
a printed circuit board (PCB) with a recess in an upper surface of the PCB;
a ball grid array (BGA) substrate coupled to the upper surface of the PCB;
a system on a chip (SoC) coupled to a lower surface of the BGA substrate, wherein at least a portion of the SoC is located in the recess in the upper surface of the PCB, and wherein the SoC is positioned between the upper surface in the recess of the PCB and the lower surface of the BGA substrate;
a voltage regulator coupled to the lower surface of the BGA substrate, wherein at least a portion of the voltage regulator is located in the recess in the upper surface of the PCB; and
at least one memory die attached to an upper surface of the BGA substrate with a plurality of terminals.
2. The assembly of claim 1 , wherein the SoC comprises a graphics controller, a central processing unit, one or more hardware accelerators, one or more information routers, and a memory subsystem controller and fabric.
3. The assembly of claim 2 , wherein at least one of hardware accelerators comprises an image processing accelerator.
4. The assembly of claim 2 , wherein at least one of hardware accelerators comprises a video encoder/decoder.
5. The assembly of claim 1 , further comprising a heat sink material coupled to a lower surface of the SoC.
6. The assembly of claim 1 , further comprising a power delivery system coupled to the upper surface of the BGA substrate.
7. A semiconductor device package assembly, comprising:
a printed circuit board (PCB);
a ball grid array (BGA) substrate coupled to an upper surface of the PCB;
a system on a chip (SoC) positioned between the BGA substrate and the PCB and coupled to a lower surface of the BGA substrate, the SoC comprising a graphics controller, a central processing unit, one or more hardware accelerators, one or more information routers, and a memory subsystem controller and fabric;
a voltage regulator positioned between the BGA substrate and the PCB and coupled to the lower surface of the BGA substrate; and
at least one memory die attached to an upper surface of the BGA substrate with a plurality of terminals.
8. The assembly of claim 7 , wherein at least a portion of the SoC is positioned below the upper surface of the PCB.
9. The assembly of claim 7 , wherein the PCB comprises a hole through the PCB, and wherein at least a portion of the SoC is positioned in the hole.
10. The assembly of claim 7 , further comprising a heat sink material attached to a lower surface of the SoC and a lower surface of the voltage regulator.
11. The assembly of claim 9 , wherein the PCB comprises a hole through the PCB, and wherein at least a portion of the SoC, at least a portion of the voltage regulator, and at least a portion of the heat sink material are positioned in the hole.
12. A semiconductor device package assembly, comprising:
a printed circuit board (PCB) with a recess on an upper surface of the PCB;
a ball grid array (BGA) substrate coupled to the upper surface of the PCB;
a system on a chip (SoC) coupled to a lower surface of the BGA substrate, wherein at least a portion of the SoC is located in the recess on the upper surface of the PCB;
a voltage regulator coupled to the lower surface of the BGA substrate; and
at least one memory die coupled to an upper surface of the BGA substrate.
13. The assembly of claim 12 , wherein the voltage regulator is located between the BGA substrate and the PCB with at least a portion of the voltage regulator being located in the recess on the upper surface of the PCB.
14. The assembly of claim 12 , wherein the voltage regulator comprises inductors, capacitors, and resistors to provide power to the entire assembly.
15. The assembly of claim 12 , wherein the SoC and the voltage regulator are at most about 5 mm away from each other.
16. The assembly of claim 12 , further comprising a power delivery system coupled to the upper surface of the BGA substrate.
17. The assembly of claim 12 , wherein the SoC comprises a graphics controller, a central processing unit, one or more hardware accelerators, one or more information routers, and a memory subsystem controller and fabric.
18. The assembly of claim 12 , further comprising a heat sink material attached to a lower surface of the SoC and a lower surface of the voltage regulator.