Reliable set operation for phase-change memory cell
View Patent ↗A Phase-Change Memory (PCM) device and a method of writing data to the PCM device are described. The PCM device includes a multi-phase data storage cell having at least a Set state and a Reset state that may be established using a heater configured to heat the data storage cell. A memory interface may be coupled with the heater configured to write data to the data storage cell, the data being represented by the Set or the Reset states. A write Reset pulse is used to place the data storage cell in the Reset state corresponding to a read value that is less than a read threshold. A write Set pulse that is a predetermined function of the write Reset pulse is used to place the data storage cell in the Set state. The PCM device may include additional intermediate states that enable each data storage cell to store two or more bits of information. Other embodiments may be described and claimed.
1. A phase change memory (PCM) device comprising:
a phase change data storage cell;
a heating component configured to heat the storage cell; and
a memory interface configured to apply at least one of a write Reset pulse or a write Set pulse to the heating component, wherein:
the write Reset pulse is configured to place the data storage cell in a Reset state; and
the write Set pulse is configured to place the data storage cell in a Set state, the write Set pulse comprising:
a high value pulse portion, the high value pulse portion determined based on the write Reset pulse for the data storage cell; and
a down sweep pulse portion, the down sweep pulse portion continually decreasing from the high value pulse portion and applied at least until the data storage cell is in the Set state.
2. The PCM device of claim 1 , wherein the down sweep pulse portion is applied until a read current of the data storage cell is above a read current threshold.
3. The PCM device of claim 2 wherein a time duration of the down sweep pulse portion is at least a predetermined time duration determined to provide a read current of the data storage cell above the read current threshold.
4. The PCM device of claim 2 , wherein the read current of the data storage cell is periodically compared to the read current threshold to determine when the read current of the data storage cell is above the read current threshold.
5. The PCM device of claim 1 , wherein the phase change data storage cell is a multi-phase data storage cell, the multi-phase data storage cell further comprising an intermediate state, and wherein the memory interface is configured to apply the down sweep pulse portion until the data storage cell is in the intermediate state.
6. The PCM device claim 5 , wherein a read current of the data storage cell is periodically compared to a read current threshold for the intermediate state to determine when a read current of the data storage cell is above the read current threshold for the intermediate state.
7. The PCM device of claim 1 , wherein the high value pulse portion of the write Set pulse is equal to a predetermined proportion of the write Reset pulse.
8. The PCM device of claim 1 , further comprising a plurality of the phase change data storage cells, wherein each of the plurality of the data storage cells has a particular write Set pulse determined based on a particular Reset pulse used to place that particular data storage cell in the Reset state, and wherein the Reset and Set pulses for each corresponding particular data storage cell are determined independently of Reset and Set pulses for other data storage cells.
9. A method of writing data to a phase change memory (PCM) device, the method comprising:
applying a write Reset pulse to place a data storage cell of the PCM device in a Reset state; and
applying a write Set pulse to place the data storage cell in a Set state, the write Set pulse comprising:
a high value pulse portion, the high value pulse portion determined based on the write Reset pulse; and
a down sweep pulse portion, the down sweep pulse portion continually decreasing from the high value pulse portion and applied at least until the data storage cell is in the Set state.
10. The method of claim 9 , wherein the down sweep pulse portion is applied until a read current of the data storage cell is above a read current threshold.
11. The method of claim 10 , wherein the read current of the data storage cell is periodically compared to the read current threshold to determine when the read current of the data storage cell is above the read current threshold.
12. The method of claim 10 , wherein a time duration of the down sweep pulse portion is at least a predetermined time duration for the data storage cell to have a read current above the read current threshold.
13. The method of claim 9 , further comprising placing the data storage cell of the PCM device in an intermediate state, wherein the down sweep pulse portion is applied until the data storage cell is in the intermediate state.
14. The method claim 13 , wherein a read current of the data storage cell is periodically compared to a read current threshold for the intermediate state to determine when the read current of the data storage cell is above the read current threshold for the intermediate state.
15. The method of claim 9 , wherein the write Set pulse is equal to a predetermined proportion of the write Reset pulse.
16. The method of claim 9 , further comprising:
applying write Reset pulses to place a plurality of data storage cells of the PCM device in the Reset state; and
applying write Set pulses to place the plurality of data storage cells of the PCM device in the Set state,
wherein each of the plurality of the data storage cells has a particular write Set pulse determined based on a particular Reset pulse used to place that particular data storage cell in the Reset state, and wherein the Reset and Set pulses for each corresponding particular data storage cell are determined independently of Reset and Set pulses for other data storage cells.
17. A memory array comprising:
a plurality of phase change data storage cells; and
a plurality of heating components configured to heat the plurality of data storage cells by receiving at least one of a write Reset pulse or a write Set pulse, wherein:
the write Reset pulse is configured to place a data storage cell in a Reset state; and
the write Set pulse is configured to place the data storage cell in a Set state, the write Set pulse comprising:
a first high value pulse portion, the first high value pulse portion equal to a first predetermined proportion of the write Reset pulse; and
a first down sweep pulse portion, the first down sweep pulse portion continually decreasing from the first high value pulse portion and applied at least until the data storage cell is in the Set state.
18. The memory array of claim 17 , wherein the data storage cell further comprises an intermediate state.
19. The memory array of claim 18 , wherein the heating components are further configured to heat the data storage cells by receiving a write intermediate pulse, the write intermediate pulse configured to place the data storage cell in the intermediate state, the write intermediate pulse comprising:
a second high value pulse portion, the second high value pulse portion equal to a second predetermined proportion of the write Reset pulse; and
a second down sweep pulse portion,
wherein the first predetermined proportion of the write Reset pulse for placing the data storage cell in the Set state is larger than the second predetermined proportion of the write Reset pulse for placing data storage cell in the intermediate state.
20. The memory array of claim 19 , wherein a time duration of the first down sweep pulse portion is longer than a time duration of the second down sweep pulse portion.