Method of manufacturing a semiconductor device including dummy regions and dummy wirings
View Patent ↗There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP 1 of relatively wider area and the second dummy pattern DP 2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP 1 occupy a relatively wide region among the dummy region FA.
1. A method for manufacturing a semiconductor device, comprising steps of:
(a) forming grooves in a semiconductor substrate such that the grooves define an active region, a plurality of first dummy regions and a plurality of second dummy regions;
(b) filling element isolation insulating films in the grooves;
(c) forming semiconductor elements in the active region;
(d) forming a first interlayer insulation film over the semiconductor elements, the active region, the first dummy regions and the second dummy regions;
(e) forming a first wiring, a plurality of first dummy wirings and a plurality of second dummy wirings over the first interlayer insulation film, respectively; and
(f) forming a second interlayer insulation film over the first interlayer insulation film, the first wiring, the first dummy wirings and the second dummy wirings,
wherein the first wiring is electrically connected with the semiconductor elements,
wherein the first dummy wirings and the second dummy wirings are not electrically connected with the semiconductor elements,
wherein a planar size of each of the first dummy regions is larger than a planar size of each of the second dummy regions,
wherein each of the first dummy regions is arranged with the same pitch,
wherein each of the second dummy regions is arranged with the same pitch,
wherein a planar size of each of the first dummy wirings is larger than a planar size of each of the second dummy wirings,
wherein each of the first dummy wirings is arranged with the same pitch,
wherein each of the second dummy wirings is arranged with the same pitch,
wherein the second dummy wirings are arranged next to the first wiring, and between the first wiring and the first dummy wirings,
wherein the pitch of the first dummy regions is larger than the pitch of the second dummy regions,
wherein the pitch of the first dummy wirings is larger than the pitch of the second dummy wirings,
wherein, in planar view, the first and second wirings are arranged over the first and second dummy regions,
wherein the first wiring, the first dummy wirings and the second dummy wirings are formed of a copper as a major component, and
wherein the semiconductor elements comprise MOSFETs.
2. A method for manufacturing a semiconductor device according to the claim 1 ,
wherein, in planar view, the first dummy wirings are arranged over the first dummy regions, and
wherein, in planar view, the second dummy wirings are arranged over the second dummy regions.