Apparatus and method for fast cache flushing including determining whether data is to be stored in nonvolatile memory
Apparatus, systems, and methods to manage memory operations are described. A cache controller is provided comprising logic to receive a transaction to operate on a data element in a cache memory, determine whether the data element is to be stored in a nonvolatile memory by querying a source address decoder (SAD), and, in response to a determination that the data element is to be stored in the nonvolatile memory, to forward the transaction to a memory controller coupled to the nonvolatile memory, and, in response to a determination that the data element is not to be stored in the nonvolatile memory, to drop the transaction from a cache flush procedure of the cache controller. Additionally, the cache controller may receive a confirmation signal from the memory controller that the data element was stored in the nonvolatile memory, and return a completion signal to an originator of the transaction. The cache controller may also include logic to place a processor core in a low power state.
1. A computing device, comprising:
a processor comprising multiple processing units, with each processing unit respectively including:
a core;
a cache memory;
a source address decoder; and
a cache controller coupled to the cache memory, the core, and the source address decoder, the cache controller configured to:
receive a cache transaction from the core to operate on a data element in the cache memory;
determine whether the data element is to be stored in a nonvolatile memory by querying the source address decoder; and
in response to a determination that the data element is to be stored in the nonvolatile memory, to forward the cache transaction from the cache controller over a communication bus to a memory controller coupled to the nonvolatile memory via a memory channel; and
in response to a determination that the data element is not to be stored in the nonvolatile memory, to drop the cache transaction from a cache flush procedure of the cache controller.
2. The device of claim 1 , wherein the cache controllers of the multiple processing units are structurally configured to operate in parallel with respect to one another.
3. The device of claim 1 , wherein each cache controller is further configured to:
receive a confirmation signal from the memory controller that the data element was stored in the nonvolatile memory; and
return a completion signal to the associated core.
4. The device of claim 1 , wherein each cache controller is further configured to return a completion signal to the associated core upon dropping the cache transaction.
5. The device of claim 1 , wherein each cache controller is further configured to block additional transactions on the associated core.
6. The device of claim 5 , wherein each cache controller is further configured to place the associated core in a low power state.
7. The device of claim 1 , wherein the nonvolatile memory is communicatively coupled to each processing unit.