IP Library Granted Patent US 8,877,600
Granted Patent B2
US 8,877,600 · App. 14/104,903 · Granted Nov 4, 2014

Method for manufacturing a hybrid SOI/bulk semiconductor wafer

Inventors: Claire Fenouillet-Beranger (Grenoble, FR); Stephane Denorme (Crolles, FR); Nicolas Loubet (Guilderland, NY); Qing Liu (Guilderland, NY); Emmanuel Richard (le Champ-Pres-Froges, FR); Pierre Perreau (Varces, FR)
Assignees: STMicroelectronics, Inc.; STMicroelectronics SA; STMicroelectronics (Crolles 2) SAS; Commissariat à l'Énergie Atomique et aux Énergies Alternatives
H01L21/76283
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Quick Facts
Patent No.
US 8,877,600
App. No.
14/104,903
Granted
Nov 4, 2014
Kind
B2
Abstract

A method for manufacturing a hybrid SOI/bulk substrate, including the steps of starting from an SOI wafer comprising a single-crystal semiconductor layer called SOI layer, on an insulating layer, on a single-crystal semiconductor substrate; depositing on the SOI layer at least one masking layer and forming openings crossing the masking layer, the SOI layer, and the insulating layer, to reach the substrate; growing by a repeated alternation of selective epitaxy and partial etching steps a semiconductor material; and etching insulating trenches surrounding said openings filled with semiconductor material, while encroaching inwards over the periphery of the openings.

Claims (12)

1. A method for manufacturing a hybrid SOI/bulk substrate, comprising the steps of:

a) starting from an SOI wafer comprising a single-crystal semiconductor SOI layer, on an insulating layer, on a single-crystal semiconductor substrate;

b) depositing on the SOI layer at least one masking layer and forming openings crossing the masking layer, the SOI layer, and the insulating layer, to reach the substrate;

c) growing, without forming spacers, by a repeated alternation of selective epitaxy and partial etching steps a semiconductor material, up to the desired final level; and

d) etching insulating trenches surrounding said openings filled with semiconductor material while encroaching inwards over the periphery of the openings.

2. The method of claim 1 , wherein step c) is carried on until the central portion of the upper surface of the semiconductor material is at the same level as the upper surface of the SOI layer.

3. The method of claim 1 , wherein the semiconductor material of the substrate and that of the SOI layer are silicon.

4. The method of claim 1 , wherein the thickness of the SOI layer ranges between 3 and 10 nm.

5. The method of claim 1 , wherein the thickness of the insulating layer ranges between 5 and 50 nm.

6. The method of claim 3 , wherein the masking layer comprises a stack of a layer of a silicon oxide and of a layer of a silicon nitride.

7. The method of claim 3 , further comprising, between steps a) and b), a step of forming silicon-germanium regions in portions of the SOI layer.

8. The method of claim 7 , wherein the silicon-germanium regions are formed by condensation.

Assignments (2)
CHANGE OF NAME Recorded Feb 23, 2024
From: STMICROELECTRONICS SA
To: STMICROELECTRONICS FRANCE
Reel/Frame 066663/0136 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 9, 2014
From: FENOUILLET-BERANGER, CLAIRE; DENORME, STEPHANE; LOUBET, NICOLAS; LIU, QING; RICHARD, EMMANUEL; PERREAU, PIERRE
To: STMICROELECTRONICS, INC.; STMICROELECTRONICS SA; STMICROELECTRONICS (CROLLES 2) SAS; COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
Reel/Frame 033270/0236 →
Priority Claims (1)
FR 12 62012 · Dec 13, 2012 · national
Continuity (1)
Related Publication 20140170834A1 · Jun 19, 2014