Content addressable memory with base-three numeral system
A CAM cell is disclosed that can be selectively configured to store either base-2 data words or base-3 data words. When configured to store base-3 data words, the quaternary CAM cell compares 3 comparand bits representative of a base-3 comparand value with the base-3 data value stored in the CAM cell. Storing base-3 data words in such CAM cells increases the data storage density of associated CAM arrays.
1. A content addressable memory (CAM) device including a CAM array having a plurality of quaternary CAM cells each configured to store a base-3 data value having one of four possible states represented by first and second data bits, wherein a respective CAM cell comprises:
first and second memory cells for storing the first and second data bits, respectively; and
a compare circuit, coupled to the first and second memory cells and to a match line, to selectively discharge the match line in response to a compare operation between a base-3 comparand value and the base-3 data value;
wherein the CAM array is configured to selectively store a trit of a base-3 data word or a bit of a binary data word within each CAM cell of the CAM array.
2. The CAM device of claim 1 , further comprising a first circuit coupled to the match line, and configured to pre-charge the match line during a pre-charge phase of the compare operation.
3. The CAM device of claim 1 , further comprising a first circuit coupled to the match line, and configured to pre-charge the match line to a logic high during a pre-charge phase of the compare operation.
4. The CAM device of claim 1 , wherein the compare circuit comprises three pull-down transistors, each configured to selectively discharge the match line.
5. The CAM device of claim 1 , wherein the four possible states consist of a logic 0 value, a logic 1 value, a logic 2 value, and a don't care state.
6. The CAM device of claim 1 , wherein the compare circuit comprises:
a first pull-down transistor connected between the match line and a first node, and having a gate configured to receive a first comparand bit;
a second pull-down transistor connected between the match line and a second node, and having a gate configured to receive a second comparand bit; and
a third pull-down transistor connected between the match line and a third node, and having a gate configured to receive a third comparand bit.
7. The CAM device of claim 6 , wherein the compare circuit further comprises:
a first relay transistor connected between the first node and the third node, and having a gate configured to receive a complemented second data bit; and
a second relay transistor connected between the second node and the third node, and having a gate configured to receive a complemented first data bit.
8. The CAM device of claim 7 , wherein the compare circuit further comprises:
a first gating transistor connected between the first node and ground potential, and having a gate configured to receive the first data bit; and
a second gating transistor connected between the second node and ground potential, and having, a gate configured to receive the second data bit.
9. The CAM device of claim 8 , wherein the first, second, and third pull-down transistors are each an NMOS transistor, the first and second relay transistors are each an NMOS transistor, and the first and second gating transistors are each an NMOS transistor.
10. A content addressable memory (CAM) cell configured to store a base-3 data value having one of four possible states represented by first and second data bits, wherein the CAM cell comprises:
first and second memory cells configured to store the first and second data bits, respectively; and
a compare circuit configured to compare a base-3 comparand value with the base-3 data value, and further configured to change a logic state of a match line, wherein the base-3 comparand value is provided to the CAM cell as three comparand bits.
11. The CAM cell of claim 10 , wherein the compare circuit is configured to change the logic state of the match line by discharging the match line.
12. The CAM cell of claim 10 , wherein the compare circuit is configured to change the logic state of the match line by discharging the match line after the match line has been pre-charged.
13. The CAM cell of claim 10 , wherein the compare circuit is configured to change the logic state of the match line by discharging the match line after the match line has been pre-charged to a logic high.
14. The CAM cell of claim 10 , wherein the compare circuit is configured to compare the three comparand bits with the first and second data bits at the same time.
15. The CAM cell of claim 10 , wherein the four possible states consist of a logic 0 value, a logic 1 value, a logic 2 value, and a don't care state.
16. The CAM cell of claim 10 , wherein the compare circuit comprises three pull-down transistors, each configured to selectively discharge the match line in response to a corresponding one of the three comparand bits.
17. The CAM cell of claim 10 , wherein the compare circuit comprises:
a first pull-down transistor connected between the match line and a first node, and having a gate configured to receive a first comparand bit;
a second pull-down transistor connected between the match line and a second node, and having a gate configured to receive a second comparand bit; and
a third pull-down transistor connected between the match line and a third node, and having a gate configured to receive a third comparand bit.
18. The CAM cell of claim 17 , wherein the compare circuit further comprises:
a first relay transistor connected between the first node and the third node, and having a gate configured to receive a complemented second data bit; and
a second relay transistor connected between the second node and the third node, and having a gate configured to receive a complemented first data bit.
19. The CAM cell of claim 17 , wherein the compare circuit further comprises:
a first gating transistor connected between the first node and ground potential, and having a gate configured to receive the first data bit; and
a second gating transistor connected between the second node and ground potential, and having a gate configured to receive the second data bit.