DISTURB-RESISTANT NON-VOLATILE MEMORY DEVICE AND METHOD

1 . A device including a non-volatile memory device structure, comprising:

a substrate having a surface region and comprising a plurality of transistors;

a first dielectric material overlying the surface region of the semiconductor substrate;

a first cell, the first cell comprising a first wiring structure extending in a first direction overlying the first dielectric material, a first buffer layer region comprising a p+ polycrystalline silicon containing material, a first switching region comprising an amorphous silicon material, and a second wiring structure extending in a second direction orthogonal to the first direction;

a second cell, the second cell comprising the first wiring structure, a second buffer layer region comprising a p+ polycrystalline silicon containing material, a second switching region comprising an amorphous silicon material, and a third wiring structure separated from the second wiring structure and parallel to the second wiring structure; and

a second dielectric material disposed at least in a region between the first switching region and the second switching region to electrically and physically isolate the first switching region and the second switching region;

wherein at least one transistor from the plurality of transistors is coupled to the first cell.

2 . The device of claim 1 wherein the first cell and the second cell are provided in an N by M interconnected crossbar array.

3 . The device of claim 1 wherein the second dielectric material is further disposed in a first region between the first buffer layer region and the second buffer layer region, and in a second region between the second wiring structure and the third wiring structure.

4 . The device of claim 1 further comprising:

a third dielectric material having an upper surface disposed on top of the first switching region and the second switching region, wherein the third dielectric material comprises a first via in the upper surface exposing a portion of the first switching region, wherein the third dielectric material comprises a second via in the upper surface exposing a portion of the second switching region; and

wherein the second wiring structure is coupled to the portion of the first switching region within the first via; and

wherein the third wiring structure is coupled to the portion of the second switching region within the second via.

5 . The device of claim 1

wherein the first buffer layer region is coupled to the first wiring structure at a first region having a first lateral area;

wherein the first switching region is coupled to the second wiring structure at a second region having a second lateral area; and

wherein the first lateral area is different from the second lateral area.

6 . The device of claim 1 wherein the plurality of transistors comprises a controller.

7 . The device of claim 1 wherein the amorphous silicon material of the second cell and the amorphous silicon material of the first cell are formed from a common amorphous silicon material.

8 . The device of claim 1 wherein the second wiring comprises a material selected from a group consisting of: silver, gold, platinum, palladium.

9 . The device of claim 8 wherein the second wiring also comprises a material selected from a group consisting of: tungsten, copper, and aluminum.

10 . The device of claim 1 wherein a pattern for the first switching region is not identical to a pattern for the first buffer layer region.

11 . The device of claim 1 further comprising:

a third cell, the third cell comprising a fourth wiring structure extending in the first direction overlying the first dielectric material, a third buffer layer region comprising a p+ polycrystalline silicon containing material, a third switching region comprising an amorphous silicon material, and the second wiring structure extending in the second direction orthogonal to the first direction;

a fourth cell, the fourth cell comprising the fourth wiring structure extending in the first direction overlying the first dielectric material, a fourth buffer layer region comprising a p+ polycrystalline silicon containing material, a fourth switching region comprising an amorphous silicon material, and the third wiring structure extending in the second direction orthogonal to the first direction;

wherein the second dielectric material is disposed at least in a region between the third switching region and the fourth switching region to electrically and physically isolate the third switching region and the fourth switching region; and

wherein the second dielectric material is disposed at least in a region between the first switching region and the third switching region to electrically and physically isolate the first switching region and the third switching region.

12 . The device of claim 1 wherein the amorphous silicon material is configured to allow metal particles from the second wiring structure to diffuse therein.

13 . A method for fabricating a device including a non-volatile memory device structure, comprising:

receiving a substrate having a surface region and comprising a plurality of transistors;

depositing a first dielectric material overlying the surface region of the semiconductor substrate;

forming a first cell, the first cell comprising a first wiring structure extending in a first direction overlying the first dielectric material, a first buffer layer region comprising a p+ polycrystalline silicon containing material, a first switching region comprising an amorphous silicon material, and a second wiring structure extending in a second direction orthogonal to the first direction;

forming a second cell, the second cell comprising the first wiring structure, a second-buffer layer region comprising a p+ polycrystalline silicon containing material, a second switching region comprising an amorphous silicon material, and a third wiring structure separated from the second wiring structure and parallel to the second wiring structure; and

forming a second dielectric material at least in a region between the first switching region and the second switching region to electrically and physically isolate the first switching region and the second switching region;

wherein at least one transistor from the plurality of transistors is coupled to the first cell.

14 . The method of claim 13 wherein forming the first cell comprises:

forming the first wiring structure extending in the first direction overlying the first dielectric material;

forming the first buffer layer region comprising the p+ polycrystalline silicon containing material on top of the first wiring structure;

forming the first switching region comprising the amorphous silicon material on top of the first buffer layer region; and

forming the second wiring structure extending in the second direction orthogonal to the first direction on top of the first switching region.

15 . The method of claim 14 wherein forming the first buffer layer region comprises:

depositing a layer of p+ polycrystalline silicon containing material on top of the first wiring structure; and

etching away portions of the layer of p+ polycrystalline silicon containing material to form the first buffer layer region.

16 . The method of claim 14 wherein forming the switching region comprises:

depositing a layer of switching material on top of the first buffer layer region; and

etching away portions of the layer of switching material to form the first switching region.

17 . The method of claim 14 wherein forming the second wiring structure comprises:

depositing a layer of metal on top of a portion of the first switching region; and

etching away portions of the layer of metal to form the second wiring structure.

18 . The method of claim 17 wherein the metal is selected from a group consisting of: silver, gold, platinum, palladium.

19 . The method of claim 18 wherein the metal also comprises a material selected from a group consisting of: tungsten, copper, and aluminum.

20 . The method of claim 17

wherein the first buffer layer region is coupled to the first wiring structure at a first region having a first contact area;

wherein the first switching region is coupled to the second wiring structure at a second region having a second contact area; and

wherein the first contact area is different from the second contact area.