IP Library › Granted Patent US 9,093,434
Granted Patent B2
US 9,093,434 · App. 14/110,131 · Granted Jul 28, 2015

Semiconductor device and method for manufacturing semiconductor device

Inventors: Akihiro Kimura (Kyoto, JP); Takeshi Sunaga (Kyoto, JP); Shouji Yasunaga (Kyoto, JP); Akihiro Koga (Kyoto, JP)
Assignee: ROHM CO., LTD.
H01L21/4825H01L21/561H01L21/565H01L23/3107H01L23/3142H01L23/36H01L23/4334H01L23/49541H01L23/49551H01L23/49568H01L23/49575H01L23/49586H01L24/49H01L24/32H01L24/48H01L24/83H01L24/85H01L2224/291H01L2224/32245H01L2224/48091H01L2224/48137H01L2224/48247H01L2224/48472H01L2224/49171H01L2224/49173H01L2224/49175H01L2224/49177H01L2224/73265H01L2224/83192H01L2224/85H01L2224/92247H01L2924/00013H01L2924/01029H01L2924/1305H01L2924/13055H01L2924/13091
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Quick Facts
Patent No.
US 9,093,434
App. No.
14/110,131
Granted
Jul 28, 2015
Kind
B2
Abstract

A method includes the steps of: preparing a lead frame including a plurality of die pads, and preparing a plurality of semiconductor chips; disposing each of the semiconductor chips on a respective one of the die pads; forming a sealing resin to cover the die pads and the semiconductor chips; and attaching a heat dissipation plate to the die pads by pressing the heat dissipation plate against the die pads via a resin sheet which is an adhesive layer after the sealing resin is formed.

Claims (33)

1. A semiconductor device comprising:

a plurality of die pads each having a bottom surface;

a plurality of semiconductor chips each of which is disposed on a respective one of the die pads;

a sealing resin covering top surfaces of the plurality of die pads and the semiconductor chips, the sealing resin extending about the sides of and extending below the bottom surfaces of the plurality of die pads to form a recess comprised of the extended portion of the sealing resin as a recess side surface, the recess exposing the bottom surfaces of the plurality of die pads within the recess;

a heat dissipation plate configured for insertion into and disposed in the recess; and

an intermediate layer including a plurality of first portions;

wherein each of the first portions bonds a respective one of the plurality of die pads to the heat dissipation plate and is disposed between the respective one of the die pads and the heat dissipation plate, and wherein the recess includes a recess side surface and a recess bottom surface spaced apart from the heat dissipation plate.

2. The semiconductor device according to claim 1 , wherein at least one of the heat dissipation plate or the first portions have electrical insulating properties.

3. The semiconductor device according to claim 1 , wherein the bottom surface of each of the plurality of die pads includes an irregular surface with which a corresponding one of the first portions is in contact.

4. The semiconductor device according to claim 1 , wherein the recess includes a recess bottom surface, and the die pads are exposed from the recess bottom surface.

5. The semiconductor device according to claim 1 , wherein the intermediate layer includes an electrically insulating portion disposed between the recess side surface and the side surface of the heat dissipation plate and also disposed between the recess bottom surface and a part of the top surface of the heat dissipation plate.

6. The semiconductor device according to claim 1 , wherein the intermediate layer includes a second portion connected to the first portions, the heat dissipation plate is made of a conductor, and the first portions and the second portion are made of a same electrically insulating material.

7. The semiconductor device according to claim 1 , wherein the heat dissipation plate is made of a ceramic material, and the first portions are spaced apart from each other and made of a conductor.

8. The semiconductor device according to claim 1 , wherein the sealing resin includes a resin bottom surface, the recess is indented from the resin bottom surface, and the heat dissipation plate includes a portion projecting from the resin bottom surface.

9. The semiconductor device according to claim 4 , wherein the recess bottom surface is an irregular surface.

10. The semiconductor device according to claim 4 , wherein the sealing resin includes a plurality of bar portions standing from the recess bottom surface, each of the bar portions being positioned between the heat dissipation plate and the recess side surface.

11. The semiconductor device according to claim 4 , wherein the sealing resin includes a projection projecting from the recess bottom surface, the projection being in contact with the heat dissipation plate.

12. The semiconductor device according to claim 6 , further comprising a filler contained in the first portions and the second portion.

13. The semiconductor device according to claim 6 , wherein the conductor is selected from the group consisting of aluminum, copper and iron.

14. The semiconductor device according to claim 6 , wherein the electrically insulating material is a thermoplastic resin.

15. The semiconductor device according to claim 7 , wherein the ceramic material is selected from the group consisting of alumina, aluminum nitride and silicon nitride.

16. The semiconductor device according to claim 7 , wherein the conductor is selected from the group consisting of silver, gold and copper.

17. A semiconductor device comprising:

a plurality of die pads each having a bottom surface;

a plurality of semiconductor chips each of which is disposed on a respective one of the die pads;

a sealing resin including a recess that exposes a plurality of the die pads and covering the plurality of die pads and the semiconductor chips;

a heat dissipation plate disposed in the recess and comprising a top surface and a side surface; and

an intermediate layer including a plurality of first portions;

wherein each of the first portions bonds a respective one of the plurality of die pads to the top surface of the heat dissipation plate and is disposed between the respective one of the die pads and the heat dissipation plate, and wherein the recess includes a recess side surface and a recess bottom surface each spaced apart from the heat dissipation plate,

wherein the intermediate layer includes an electrically insulating portion disposed between the recess side surface and the side surface of the heat dissipation plate and also disposed between the recess bottom surface and a part of the top surface of the heat dissipation plate.

18. The semiconductor device according to claim 17 , wherein the die pads are exposed from the recess bottom surface.

19. The semiconductor device according to claim 17 , wherein the sealing resin includes a resin bottom surface, the recess is indented from the resin bottom surface, and the heat dissipation plate includes a portion projecting from the resin bottom surface.

20. The semiconductor device according to claim 18 , wherein the recess bottom surface is an irregular surface.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 9, 2013
From: KIMURA, AKIHIRO; SUNAGA, TAKESHI; YASUNAGA, SHOUJI; KOGA, AKIHIRO
To: ROHM CO., LTD.
Reel/Frame 031374/0984 →
Priority Claims (6)
JP 2011-082405 · Apr 4, 2011 · national
JP 2011-082560 · Apr 4, 2011 · national
JP 2011-104349 · May 9, 2011 · national
JP 2011-105511 · May 10, 2011 · national
JP 2011-105512 · May 10, 2011 · national
JP 2011-105513 · May 10, 2011 · national
Continuity (1)
Related Publication 20140027891A1 · Jan 30, 2014