Layered semiconductor substrate with reduced bow having a group III nitride layer and method for manufacturing it

1. A layered semiconductor substrate comprising

a) a monocrystalline first layer ( 1 ) containing at least 80% silicon and having a first thickness and a first lattice constant (a 1 ), the first lattice constant (a 1 ) being determined by a first dopant element and a first dopant concentration and

b) a monocrystalline second layer ( 2 ) containing at least 80% silicon and having a second thickness and a second lattice constant (a 2 ), the second lattice constant (a 2 ) being determined by a second dopant element and a second dopant concentration, the second layer ( 2 ) being in direct contact with the first layer, and

c) a monocrystalline third layer ( 4 ) comprising a group III nitride, such that the second layer is located between the first layer and the third layer,

wherein the second lattice constant (a 2 ) is larger than the first lattice constant (a 1 ), wherein the crystal lattice of the first layer ( 1 ) and the second layer ( 2 ) are lattice-matched so that the second layer ( 2 ) is strained, and wherein the bow of the layered semiconductor substrate is in the range from −50 μm to 50 μm, and

wherein the first and second dopant elements are identical and have a smaller covalent atomic radius than silicon, or wherein the first and second dopant element is antimony, or wherein the first dopant element has a smaller covalent atomic radius than silicon and the second dopant element has a larger covalent atomic radius than silicon.

2. The layered semiconductor substrate of claim 1 , wherein the first and second dopant elements are elements having a smaller covalent atomic radius than silicon and wherein the first dopant concentration is higher than the second dopant concentration.

3. The layered semiconductor substrate of claim 2 , wherein the first and second dopant element comprises boron.

4. The layered semiconductor substrate of claim 2 , wherein the second dopant concentration is zero.

5. The layered semiconductor substrate of claim 3 , wherein the second dopant concentration is zero.

6. The layered semiconductor substrate of claim 1 , wherein the first and second dopant element is antimony and wherein the second dopant concentration is higher than the first dopant concentration.

7. The layered semiconductor substrate of claim 6 , wherein the first dopant concentration is zero.

8. The layered semiconductor substrate of claim 1 , wherein the first dopant element is boron and the second dopant element is germanium or antimony.

9. A method for manufacturing a layered semiconductor substrate of claim 1 , comprising the steps of

a) growing a single crystal containing at least 80% silicon and a first dopant element having the first dopant concentration, the single crystal having a first lattice constant,

b) slicing at least one wafer from the single crystal,

c) reducing the thickness of the wafer to a first thickness, the wafer constituting the first layer ( 1 ),

d) epitaxially depositing the second layer ( 2 ) on one of the surfaces of the wafer, and

e) epitaxially depositing the third layer ( 4 ) comprising a group III nitride.

10. The layered semiconductor substrate of claim 1 , wherein the first layer comprises a silicon wafer with a crystal orientation of (111).

11. The method of claim 9 , wherein the first layer comprises a silicon wafer with a crystal orientation of (111).

12. The layered semiconductor substrate of claim 1 , wherein the bow is within the range of −10 μm to 10 μm.

13. The method of claim 9 , wherein the bow is within the range of −10 μm to 10 μm.