Zero sum signaling in a digital system environment
View Patent ↗Zero sum signaling schemes utilize coding across data words to allow the use of single-ended buffers while mitigating simultaneous switching noise (SSN) in digital systems. Zero sum signaling may include balanced zero sum coding (target disparity=0) and nearly balanced zero sum coding (target disparity=±d). Zero sum signaling may reduce simultaneous switching noise as compared to single-ended signaling while allowing a reduction in the number of physical channels (e.g. circuit board traces) by nearly a factor of two as compared to differential signaling.
1. A system comprising:
a plurality of devices that communicate using n-bit data words, each associated with a different one of a plurality of encoders and a different one of a plurality of decoders;
wherein each of the plurality of encoders receives an n-bit data word from the associated device and encodes the n-bit data word into a corresponding (n+p)-bit data word comprised of an n-bit modified data word and a p-bit parity word, the n-bit modified data word having a number of ones and a number of zeroes, wherein the number of ones is within a disparity ±d as compared to the number of zeroes, and wherein the number of bits p in the p-bit parity word decreases as an absolute value of the disparity ±d increases; and
a plurality of interconnects that route the (n+p)-bit modified data words between the plurality of devices; and
wherein each of the plurality of decoders receives one or more of the (n+p)-bit modified data words and decodes the received one or more of the (n+p)-bit modified data words into the corresponding n-bit data words for receipt by the associated one of the plurality of devices.
2. The system of claim 1 wherein the disparity d is any positive integer.
3. The system of claim 1 wherein the disparity d is one of ±2 or ±4.
4. The system of claim 1 wherein at least one of the plurality of devices is a processor and at least one of the plurality of devices is a memory.
5. The system of claim 1 wherein the disparity ±d equals zero.
6. The system of claim 1 wherein the (n+p)-bit data word is a balanced (n+p)-bit data word, and the n-bit modified data word includes an equal number of ones and zeroes.
7. The system of claim 1 wherein a number of interconnects in the plurality of interconnects is relatively lower when the disparity d is non-zero as compared to when disparity ±d equals zero.
8. The system of claim 1 wherein the encoder successively complements one bit of the n-bit data word until the n-bit modified data word having the number of ones within the disparity ±d as compared to the number of zeroes code is achieved.
9. The system of claim 8 wherein the encoder assigns the p-bit parity word based on how many bits of the n-bit data word are complemented to achieve the n-bit modified data word having a number of ones within the disparity ±d as compared to the number of zeroes.
10. A method comprising:
generating an n-bit data word at a first device;
encoding the n-bit data word into a corresponding (n+p)-bit data word comprised of an n-bit modified data word and a p-bit parity word, the n-bit modified data word having a number of ones and a number of zeroes, wherein the number of ones is within a disparity ±d as compared to the number of zeroes and wherein a number of bits p in the p-bit parity word decreases as an absolute value of the disparity ±d increases;
transmitting the (n+p)-bit data word; and
decoding the (n+p)-bit data word into the corresponding n-bit data word for receipt by the second device.
11. The method of claim 10 wherein encoding the n-bit data word into a corresponding (n+p)-bit data word further includes successively complementing one bit of the n-bit data word until the n-bit modified data word having a number of ones within the disparity ±d as compared to the number of zeroes code is achieved.
12. The method of claim 11 further comprising assigning the p-bit parity word based on how many bits of the n-bit data word are complemented to achieve the n-bit modified data word having a number of ones within the disparity ±d as compared to the number of zeroes.
13. A system comprising:
a first device and a second device that communicate using n-bit data words;
an encoder associated with a first processing element that receives an n-bit data word from the first processing element and encodes the n-bit data word into a corresponding (n+p)-bit data word comprised of an n-bit modified data word and a p-bit parity word, the n-bit modified data word having a number of ones and a number of zeroes, wherein the number of ones is within a disparity ±d as compared to the number of zeroes, and wherein a number of bits p in the p-bit parity word decreases as an absolute value of the disparity ±d increases; and
a decoder associated with a second processing element that decodes the (n+p)-bit data word into the corresponding n-bit data word for receipt by a second processing element.
14. The system of claim 13 wherein the disparity ±d is any integer.
15. The system of claim 13 wherein the disparity ±d is one of ±2 or ±4.
16. The system of claim 13 wherein the first device is one of a processing element and a memory.
17. A method comprising:
generating an n-bit data word at a first device;
encoding the n-bit data word into a corresponding (n+p)-bit data word comprised of an n-bit modified data word and a p-bit parity word, the n-bit modified data word having a number of ones and a number of zeroes, wherein the number of ones is within a disparity ±d as compared to the number of zeroes and wherein a number of bits p in the p-bit parity word is relatively lower when the disparity d is non-zero as compared to when disparity ±d equals zero;
transmitting the (n+p)-bit data word; and
decoding the (n+p)-bit data word into the corresponding n-bit data word for receipt by the second device.
18. A system comprising:
a first device and a second device that communicate using n-bit data words;
an encoder associated with a first processing element that receives an n-bit data word from the first processing element and encodes the n-bit data word into a corresponding (n+p)-bit data word comprised of an n-bit modified data word and a p-bit parity word, the n-bit modified data word having a number of ones and a number of zeroes, wherein the number of ones is within a disparity ±d as compared to the number of zeroes, and wherein a number of bits p in the p-bit parity word is relatively lower when the disparity d is non-zero as compared to when disparity ±d equals zero; and
a decoder associated with a second processing element that decodes the (n+p)-bit data word into the corresponding n-bit data word for receipt by a second processing element.
19. A system comprising:
a plurality of devices that communicate using n-bit data words, each associated with a different one of a plurality of encoders and a different one of a plurality of decoders;
wherein each of the plurality of encoders receives an n-bit data word from the associated device and encodes the n-bit data word into a corresponding (n+p)-bit data word comprised of an n-bit modified data word and a p-bit parity word, the n-bit modified data word having a number of ones and a number of zeroes, wherein the number of ones is within a disparity ±d as compared to the number of zeroes, and wherein the number of bits p in the p-bit parity word is relatively lower when the disparity d is non-zero as compared to when disparity ±d equals zero; and
a plurality of interconnects that route the (n+p)-bit modified data words between the plurality of devices; and
wherein each of the plurality of decoders receives one or more of the (n+p)-bit modified data words and decodes the received one or more of the (n+p)-bit modified data words into the corresponding n-bit data words for receipt by the associated one of the plurality of devices.