Error correction in non
View Patent ↗Apparatus, systems, and methods for error correction in memory are described. In one embodiment, a memory controller comprises logic to receive a read request for data stored in a memory, retrieve the data and at least one associated error correction codeword, wherein the data and an associated error correction codeword is distributed across a plurality of memory devices in memory, apply a first error correction routine to decode the error correction codeword retrieved with the data and in response to an uncorrectable error in the error correction codeword, apply a second error correction routine to the plurality of devices in memory. Other embodiments are also disclosed and claimed.
1. A memory controller comprising logic to:
receive a read request for read data stored in a plurality of memory devices, wherein a single error correction codeword is distributed across the plurality of memory devices and is associated with all the read data stored in the plurality of memory devices;
retrieve the read data and the error correction codeword;
apply a first error correction routine to decode the error correction codeword; and
in response to an uncorrectable error in the error correction codeword, apply a second error correction routine to the plurality of memory devices.
2. The memory controller of claim 1 , wherein:
the error correction codeword is a Bose-Chaudhuri-Hocquenghem (BCH) error correction code; and
at least one memory device comprises a bitwise XOR of the contents of the plurality of memory devices.
3. The memory controller of claim 2 , wherein the second error correction routine comprises logic to sequentially:
select a memory device;
perform a bitwise XOR operation to recover a copy of the contents of the selected memory device; and
perform an error correction routine on the error correction codeword using the copy of the contents of the selected memory device.
4. The memory controller of claim 3 , further comprising logic to:
return the read data in response to a successful recovery of the error correction codeword using the copy of the contents of the selected memory device.
5. The memory controller of claim 3 , further comprising logic to:
return an error in response to an unsuccessful recovery of the error correction codeword using the copy of the contents of the selected memory device.
6. The memory controller of claim 1 , wherein:
the error correction codeword is a Reed-Solomon (RS) error correction code.
7. The memory controller of claim 6 , wherein the second error correction routine comprises logic to sequentially:
select a memory device;
mark contents of the selected memory device as erased symbols; and
perform an RS error correction routine on the error correction codeword using the copy of the contents of the selected memory device.
8. The memory controller of claim 7 , further comprising logic to:
return the read data in response to a successful recovery of the error correction codeword using the copy of the contents of a selected memory device.
9. The memory controller of claim 8 , further comprising logic to:
invoke an error routine in response to an unsuccessful recovery of the error correction codeword using the copy of the contents of the selected memory device.
10. An electronic device comprising:
a processor; and
a memory controller comprising logic to:
receive a read request for read data stored in a plurality of memory devices wherein a single error correction codeword is distributed across the plurality of memory devices and is associated with all the read data stored in the plurality of memory devices;
retrieve the read data and the error correction codeword;
apply a first error correction routine to decode the error correction codeword; and
in response to an uncorrectable error in the error correction codeword, apply a second error correction routine to the plurality of memory devices.
11. The electronic device of claim 10 , wherein:
the error correction codeword is a Bose-Chaudhuri-Hocquenghem (BCH) error correction code; and
at least one memory device comprises a bitwise XOR of the contents of the plurality of memory devices.
12. The electronic device of claim 11 , wherein the second error correction routine comprises logic to sequentially:
select a memory device;
perform a bitwise XOR operation to recover a copy of the contents of the selected memory device; and
perform an error correction routine on the error correction codeword using the copy of the contents of the selected memory device.
13. The electronic device of claim 12 , further comprising logic to:
return the read data in response to a successful recovery of the error correction codeword using the copy of the contents of the selected memory device.
14. The electronic device of claim 12 , further comprising logic to:
return an error in response to an unsuccessful recovery of the error correction codeword using the copy of the contents of the selected memory device.
15. The electronic device of claim 10 , wherein:
the error correction codeword is a Reed-Solomon (RS) error correction code.
16. The electronic device of claim 15 , wherein the second error correction routine comprises logic to sequentially:
select a memory device;
mark contents of the selected memory device as erased symbols; and
perform an RS error correction routine on the error correction codeword using the copy of the contents of the selected memory device.
17. The electronic device of claim 16 , further comprising logic to:
return the read data in response to a successful recovery of the error correction codeword using the copy of the contents of a selected memory device.
18. The electronic device of claim 17 , further comprising logic to:
invoke an error routine in response to an unsuccessful recovery of the error correction codeword using the copy of the contents of the selected memory device.
19. A method, comprising:
receiving, in a controller, a read request for read data stored in a plurality of memory devices, wherein a single error correction codeword is distributed across the plurality of memory devices and is associated with all the read data stored in the plurality of memory devices;
retrieving the read data and the error correction codeword;
applying, in the controller, a first error correction routine to decode the error correction codeword; and
in response to an uncorrectable error in the error correction codeword, applying, in the controller, a second error correction routine to the plurality of memory devices.
20. The method of claim 19 , wherein:
the error correction codeword is a Bose-Chaudhuri-Hocquenghem (BCH) error correction code; and
at least one memory device comprises a bitwise XOR of the contents of the plurality of memory devices.
21. The method of claim 20 , wherein the second error correction routine comprises:
selecting a memory device;
performing a bitwise XOR operation to recover a copy of the contents of the selected memory device; and
performing an error correction routine on the error correction codeword using the copy of the contents of the selected memory device.
22. The method of claim 21 , further comprising:
returning the read data in response to a successful recovery of the error correction codeword using the copy of the contents of the selected memory device.
23. The method of claim 22 , further comprising:
returning an error in response to an unsuccessful recovery of the error correction codeword using the copy of the contents of the selected memory device.
24. The method of claim 19 , wherein:
the error correction codeword is a Reed-Solomon (RS) error correction code.
25. The method of claim 24 , wherein the second error correction routine comprises:
selecting a memory device;
marking contents of the selected memory device as erased symbols; and
performing an RS error correction routine on the error correction codeword using the copy of the contents of the selected memory device.