Low dropout voltage regulator integrated with digital power gate driver
Described is an apparatus which comprises: a first power supply node to supply input power supply; a power transistor coupled to the first power supply node; a multiplexer to selectively control gate terminal of the power transistor according to whether the power transistor is to operate as part of a low dropout voltage regulator (LDO-VR) or is to operate as a digital switch; and a second power supply node coupled to the power transistor, the second power supply node to provide power supply to a load from the power transistor.
1. An apparatus comprising:
a first power supply node to supply input power supply;
a power transistor coupled to the first power supply node;
a multiplexer to selectively control a gate terminal of the power transistor according to whether the power transistor is to operate as a linear analog driver of a low dropout voltage regulator (LDO-VR) or is to operate as a digital switch,
a first signal node coupled to a first input of the multiplexer to provide a first signal to control the power transistor to operate as the LDO-VR, wherein the multiplexer has a second input to receive a second signal on a second signal node to control the power transistor to operate as the digital switch; and
a second power supply node coupled to the power transistor to provide a power supply to a load from the power transistor, wherein the LDO-VR is a flipped source follower, wherein the LDO-VR comprises a capacitive multiplication compensation network that includes a capacitor coupled to the first signal node to selectively couple to the power transistor, wherein the capacitive multiplication compensation network has a capacitance caused by capacitance multiplication effect.
2. The apparatus of claim 1 , wherein the LDO-VR comprises a diode connected transistor coupled to the first power supply node and the first signal node.
3. The apparatus of claim 2 , wherein the first signal node is coupled to the gate terminal of the power transistor via the multiplexer.
4. The apparatus of claim 1 , wherein the capacitive multiplication compensation network includes a resistor coupled to the capacitor, wherein the LDO-VR comprises a first p-type transistor comprising a first terminal coupled to the first power supply, a second terminal coupled to the first signal node and a gate terminal coupled to the resistor, and wherein the LDO-VR comprises a second p-type transistor that has a first terminal coupled to the first power supply and a second terminal coupled to the first signal node to limit an AC gain of an output stage.
5. The apparatus of claim 2 , wherein the diode-connected transistor is operable to compensate for a pole movement during current demand change on the second power supply node.
6. The apparatus of claim 4 , wherein the LDO-VR comprises:
a third p-type transistor with a source terminal coupled to the second power supply node; and
an amplifier or comparator to compare a reference with a divided down voltage on the second power supply node, wherein the amplifier or comparator have an output to control a gate terminal of the third p-type transistor.
7. The apparatus of claim 6 , wherein the LDO-VR further comprises:
a first n-type transistor coupled in series with the first p-type transistor, wherein the first n-type transistor has a gate terminal controllable by a first bias voltage; and
a second n-type transistor coupled to a drain terminal of the third p-type transistor and the first n-type transistor, the second n-type transistor having a gate terminal controllable by a second bias voltage.
8. The apparatus of claim 7 , wherein the
resistor has a first terminal to receive a third bias voltage, and a second terminal,
capacitor has a first terminal coupled to the second terminal of the resistor and the gate terminal of the first p-type transistor, and capacitor has a second terminal coupled to the first signal node which is coupled to the gate terminal of the power transistor via the multiplexer and the second terminal of the first p-type transistor.
9. The apparatus of claim 1 , wherein the power transistor is a p-type transistor.
10. An apparatus comprising:
a power transistor to selectively operate as a digital power gate or as a linear analog driver of a low dropout voltage regulator (LDO-VR), wherein the LDO-VR is a flipped source follower; and
a first signal node coupled to a multiplexer to provide a first signal to control the power transistor to operate as the LDO-VR, wherein the power transistor is operable to receive a second signal on a second signal node to operate as the digital switch, wherein the LDO-VR comprises a capacitive multiplication compensation network that includes a capacitor coupled to the first signal node to selectively couple to the power transistor, and wherein the capacitive multiplication compensation network has a capacitance caused by capacitance multiplication effect.
11. The apparatus of claim 10 , wherein the power transistor is a p-type transistor.
12. The apparatus of claim 10 , wherein the LDO-VR comprises a diode-connected transistor to selectively couple to the power transistor.
13. The apparatus of claim 12 , wherein the diode-connected transistor to stabilize the LDO-VR at high current loads.
14. The apparatus of claim 12 , wherein the diode-connected transistor is a p-type transistor.
15. The apparatus of claim 12 , wherein the capacitive multiplication compensation network is coupled to the diode-connected transistor to selectively couple to the power transistor.
16. The apparatus of claim 10 , wherein the power transistor includes:
a gate terminal coupled to the multiplexer;
a source terminal coupled to a first power supply node; and
a drain terminal coupled to a second power supply node, the second power supply node for providing power to a load.
17. A system comprising:
a memory unit;
a processor coupled to the memory unit, the processor having an apparatus which comprises
a power transistor to selectively operate as a digital power gate or as a linear analog driver of a low dropout voltage regulator (LDO-VR), wherein the LDO-VR is a flipped source follower, and a first signal node coupled to a multiplexer to provide a first signal to control the power transistor to operate as the LDO-VR, wherein the power transistor is operable to receive a second signal on a second signal node to operate as the digital switch, wherein the LDO-VR comprises a capacitive multiplication compensation network that includes a capacitor coupled to the first signal node to selectively couple to the power transistor, and wherein the capacitive multiplication compensation network has a capacitance caused by capacitance multiplication effect; and
a wireless interface for communicatively coupling the processor to another device.
18. The system of claim 17 further comprises a display unit for displaying content processed by the processor.