IP Library › Granted Patent US 9,041,217
Granted Patent B1
US 9,041,217 · App. 14/133,344 · Granted May 26, 2015

Self-aligned via patterning with multi-colored photobuckets for back end of line (BEOL) interconnects

Inventors: Robert L. Bristol (Portland, OR); James M. Blackwell (Portland, OR); Alan M. Myers (Beaverton, OR); Kanwal Jit Singh (Hillsboro, OR)
Assignee: Intel Corporation
H01L23/5226H01L21/76879H01L21/76802H01L21/76808H01L21/76813H01L21/76811
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Quick Facts
Patent No.
US 9,041,217
App. No.
14/133,344
Granted
May 26, 2015
Kind
B1
Abstract

Self-aligned via patterning with multi-colored photobuckets for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate, the first layer including a first grating of alternating metal lines and dielectric lines in a first direction. The dielectric lines have an uppermost surface higher than an uppermost surface of the metal lines. A second layer of the interconnect structure is disposed above the first layer of the interconnect structure, the second layer including a second grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. The dielectric lines have a lowermost surface lower than a lowermost surface of the metal lines of the second grating. The dielectric lines of the second grating overlap and contact, but are distinct from, the dielectric lines of the first grating. First and second dielectric regions are disposed between the metal lines of the first grating and the metal lines of the second grating, and in a same plane as upper portions of the dielectric lines of the first grating and lower portions of the dielectric lines of the second grating. The first dielectric region is composed of a first cross-linked photolyzable material, and the second dielectric region is composed of a second, different, cross-linked photolyzable material.

Claims (16)

1. A method of fabricating an interconnect structure for an integrated circuit, the method comprising:

forming a mask above an ILD material layer, the mask having a plurality of spaced apart features each with a central portion and a pair of sidewall spacers;

forming, using the mask, a first plurality of trenches partially into the ILD material layer;

forming first color photobuckets in the first plurality of trenches;

forming a second mask from the mask by removing the central portion of each feature of the mask;

forming, using the second mask, a second plurality of trenches partially into the ILD material layer;

forming second, different, color photobuckets in the second plurality of trenches;

exposing, developing and removing fewer than all of the first color photobuckets by using a first lithographic exposure;

exposing, developing and removing fewer than all of the second color photobuckets by using a second, different, lithographic exposure;

forming via locations where the fewer than all of the first color photobuckets and the fewer than all of the second color photobuckets were removed; and

forming metal vias in the via locations and metal lines above the metal vias.

2. The method of claim 1 , wherein the first color photobuckets comprise 193 nm poly-methacrylate resist and the first lithographic exposure is a 193 nm exposure, and wherein the second color photobuckets comprise 248 nm poly-hydroxystyrene resist and the second lithographic exposure is a 248 nm exposure.

3. The method of claim 1 , wherein the first color photobuckets comprise a dual tone resist, the second color photobuckets comprise a single tone resist, and the first and second lithographic exposures involve irradiation by a same wavelength of light at a different dose.

4. The method of claim 1 , the method further comprising:

prior to forming metal vias in the via locations, removing all remaining of the first color and the second color photobuckets.

5. The method of claim 1 , wherein at least one of the first and second lithographic exposures is performed in the presence of a carbon-based hardmask layer, and wherein the carbon-based hardmask layer is subsequently removed using an ashing process.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 29, 2014
From: BRISTOL, ROBERT L.; BLACKWELL, JAMES M.; MYERS, ALAN M.; SINGH, KANWAL JIT
To: INTEL CORPORATION
Reel/Frame 032780/0765 →