Semiconductor device with plasma damage protecting elements
View Patent ↗An increase in chip area and a deterioration of delay performance are reduced without dummy cells or dummy gates for plasma damage, suppressing an increase in the capacitance of dummy cells or dummy gates and a deterioration of wiring. In the case where bit wires or bit contacts used for the DRAM cell region of a circuit block are used as wires and contacts for a logic circuit region, gate electrodes affected by plasma damage are automatically analyzed after the completion of placement and routing. The well contact region (well potential diffusion layer) of the logic circuit region contains dummy contacts for plasma damage.
1. A semiconductor device comprising:
a well potential diffusion layer disposed in a circuit block having a pattern of a DRAM bit line wiring layer coupled to a gate electrode of a MOSFET via a bit contact; and
dummy bit contacts disposed directly over the well potential diffusion layer in a logic circuit region,
wherein the dummy bit contacts are electrically uncoupled from a wire formed directly above the dummy bit contacts.
2. The semiconductor device according to claim 1 ,
wherein contacts to be coupled to an upper wire and the dummy bit contacts are alternately disposed over the well potential diffusion layer.
3. The semiconductor device according to claim 1 ,
wherein with respect to an active diffusion layer forming the MOSFET, the well potential diffusion layer is disposed in at least one of a direction of extending an input wire into the gate electrode and a direction of extending an output wire of the active diffusion layer, and
the dummy bit contacts are disposed over the well potential diffusion layer perpendicularly to a direction of arranging the contacts to be coupled to the upper wire.
4. The semiconductor device according to claim 1 ,
wherein the well potential diffusion layer is dot shaped, and contacts to be coupled to an upper wire and the dummy bit contacts are alternately disposed for each dot according to the dot-shaped well potential diffusion layer.
5. The semiconductor device according to claim 1 ,
wherein the dummy bit contacts are element electrically uncoupled to an upper wiring layer.
6. A semiconductor device comprising:
a memory circuit region including:
a diffusion layer;
a bit line wiring layer;
a bit contact formed between said bit line wiring layer and said diffusion layer; and
a logic circuit region including:
a well potential diffusion layer;
a first wiring layer coupled to a first transistor;
a first contact disposed directly over said well potential diffusion layer in the logic circuit region, wherein said bit line wiring layer and said first wiring layer are formed on the same wiring layer level,
wherein the first contact is electrically uncoupled from a wire formed directly above the first contact.
7. The semiconductor device according to claim 6 , wherein said first wiring layer is coupled to a gate electrode of said first transistor.
8. The semiconductor device according to claim 6 , further comprises a second contact in said logic circuit region that is disposed over said well potential diffusion layer, and a second wiring layer coupled to said well potential diffusion layer through said second contact,
wherein said second wiring layer is formed above said first wiring layer.
9. The semiconductor device according to claim 1 , wherein the dummy bit contacts are disposed in a first layer level directly over the well potential diffusion layer, and the dummy bit contacts do not contact any second layer level formed above the first layer level.
10. The semiconductor device according to claim 6 , wherein the first contact is disposed in a first layer level directly over the well potential diffusion layer, and the first contact does not contact any second layer level formed above the first layer.
11. The semiconductor device according to claim 1 , wherein the dummy bit contacts are electrically uncoupled from the wire formed directly above the dummy bit contacts in a cross-sectional view.
12. The semiconductor device according to claim 6 , wherein the first contact are electrically uncoupled from the wire formed directly above the first contact in a cross-sectional view.