Semiconductor device having metal gate and manufacturing method thereof

1. A method of manufacturing a semiconductor device having metal gate comprising:

providing a substrate having a first transistor and a second transistor formed thereon, the first transistor having a first gate trench and a first conductivity type, the second transistor having a second conductivity type, and the first conductivity type and the second conductivity type being complementary;

forming a first work function metal layer only in the first gate trench;

forming a sacrificial masking layer in the first gate trench;

removing a portion of the sacrificial masking layer to expose a portion of the first work function metal layer;

removing the exposed first work function metal layer to form a U-shaped work function metal layer, wherein topmost portions of the U-shaped work function metal layer are lower than an opening of the first gate trench; and

removing the sacrificial masking layer.

2. The method of manufacturing a semiconductor device having metal gate according to claim 1 , wherein the sacrificial masking layer is a multi-layer, and the multi-layer comprises a first masking layer and a second masking layer.

3. The method of manufacturing a semiconductor device having metal gate according to claim 2 , further comprising an etching back process for removing the portion of the sacrificial masking layer to not fill the first gate trench.

4. The method of manufacturing a semiconductor device having metal gate according to claim 3 , further comprising an etching process performed to remove the first masking layer of the sacrificial masking layer and left the second masking layer.

5. The method of manufacturing a semiconductor device having metal gate according to claim 1 , further comprising an etching back process for removing the portion of the sacrificial masking layer to not fill the first gate trench.

6. The method of manufacturing a semiconductor device having metal gate according to claim 1 , wherein the second transistor further comprises a second gate trench formed therein, and an opening width of the second gate trench is the same with an opening width of the first gate trench.

7. The method of manufacturing a semiconductor device having metal gate according to claim 6 , wherein the second gate trench and the first gate trench are formed simultaneously, and the second gate trench is filled with the sacrificial masking layer.

8. The method of manufacturing a semiconductor device having metal gate according to claim 7 , further comprising forming a first patterned photoresist exposing the sacrificial masking layer in the first gate trench on the sacrificial masking layer before removing the portion of the sacrificial masking layer.

9. The method of manufacturing a semiconductor device having metal gate according to claim 6 , further comprising:

forming a patterned hard mask on the substrate for covering and protecting the second transistor during forming the first gate trench;

removing the exposed first work function metal layer and the patterned hard mask simultaneously; and

forming the second gate trench in the second transistor.

10. The method of manufacturing a semiconductor device having metal gate according to claim 9 , wherein the first work function metal layer further comprises an overhang, and the overhang is simultaneously removed with removing the exposed first work function metal layer and the patterned hard mask.

11. The method of manufacturing a semiconductor device having metal gate according to claim 6 , further comprising sequentially forming a second work function metal layer and a filling metal layer in the first gate trench and the second gate trench.

12. The method of manufacturing a semiconductor device having metal gate according to claim 11 , wherein an upper area of the second work function metal layer in the first gate trench is wider than a lower area of the second work function metal layer.

13. The method of manufacturing a semiconductor device having metal gate according to claim 1 , further comprises a third transistor formed on the substrate, and a third gate trench is formed in the third transistor simultaneously with forming the first gate trench, wherein an opening width of the third gate trench is larger than an opening width of the first gate trench.

14. The method of manufacturing a semiconductor device having metal gate according to claim 13 , further comprises steps performed before removing the portion of the sacrificial masking layer to expose the portion of the first work function metal layer:

forming the sacrificial masking layer in the third gate trench; and

forming a second patterned photoresist on the substrate, the second patterned photoresist covering the third transistor but exposing the first transistor.

15. A method of manufacturing a semiconductor device having metal gate comprising:

providing a substrate having a first transistor and a second transistor formed thereon, the first transistor having a first gate trench formed therein, the second transistor having a second gate trench formed therein, and an opening width of the second gate trench is larger than an opening width of the first gate trench;

forming a first work function metal layer in the first gate trench;

forming a sacrificial masking layer in the first gate trench and the second gate trench;

forming a patterned photoresist covering the second transistor and exposing the sacrificial masking layer in the first gate trench on the substrate;

removing a portion of the sacrificial masking layer to expose a portion of the first work function metal layer; and

removing the exposed the first work function metal layer to form a U-shaped work function metal layer.

16. The method of manufacturing a semiconductor device having metal gate according to claim 15 , wherein the sacrificial masking layer is a multi-layer, and the multi-layer comprises a first masking and a second masking layer.

17. The method of manufacturing a semiconductor device having metal gate according to claim 16 , further comprising an etching back process for removing the portion of the sacrificial masking layer to not fill the first gate trench.

18. The method of manufacturing a semiconductor device having metal gate according to claim 17 , further comprising an etching process performed to remove the first masking layer of the sacrificial masking layer and left the second masking layer.

19. The method of manufacturing a semiconductor device having metal gate according to claim 15 , further comprising an etching back process for removing the portion of the sacrificial masking layer.

20. The method of manufacturing a semiconductor device having metal gate according to claim 15 , further comprising removing the sacrificial masking layer after forming the U-shaped work function metal layer.

21. The method of manufacturing a semiconductor device having metal gate according to claim 15 , further comprising a third transistor positioned on the substrate, the first transistor and the second transistor comprise a first conductivity type, the third transistor comprises a second conductivity type, and the first conductivity type and the second conductivity type complementary.

22. The method of manufacturing a semiconductor device having metal gate according to claim 21 , wherein the third transistor further comprises a third gate trench formed simultaneously with forming the first gate trench and the second gate trench.

23. The method of manufacturing a semiconductor device having metal gate according to claim 22 , wherein an opening width of the third gate trench is the same with the opening width of the first gate trench, and the third gate trench is filled with the sacrificial masking layer.

24. The method of manufacturing a semiconductor device having metal gate according to claim 23 , wherein the patterned photoresist covers the sacrificial masking layer in the third gate trench.

25. The method of manufacturing a semiconductor device having metal gate according to claim 22 , further comprising sequentially forming a second work function metal layer and a filling metal layer in the first gate trench, in the second gate trench and in the third gate trench.

26. The method of manufacturing a semiconductor device having metal gate according to claim 25 , wherein an upper area of the second work function metal layer in the first gate trench is wider than a lower area of the second work function metal layer.

27. The method of manufacturing a semiconductor device having metal gate according to claim 15 , wherein the first work function metal layer is simultaneously formed in the second gate trench.