IP Library › Granted Patent US 9,204,215
Granted Patent B2
US 9,204,215 · App. 14/136,484 · Granted Dec 1, 2015

One-bit digital-to-analog converter offset cancellation

Inventors: Christian Fraisse (Grenoble, FR); Angelo Nagari (Grenoble, FR)
Assignee: ST-ERICSSON SA
H04R3/00H03F3/2175H03F3/45968H03M3/384H03F2200/331H03F2200/375H03M3/50
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Quick Facts
Patent No.
US 9,204,215
App. No.
14/136,484
Granted
Dec 1, 2015
Kind
B2
Abstract

There is described Audio driver circuit comprising a main, 1-bit digital-to-analog converter, adapted to receive a 1-bit oversampled digital audio signal. Thanks to an auxiliary digital-to-analog converter which converts into the analog domain a digital offset compensation value stored in e.g. an OTP memory register 34 , and to a summing and filtering arrangement, it is possible to reduce the offset cancellation granularity in order to compensate for the offset of the main digital-to-analog converter in the output signal.

Claims (24)

1. Audio driver circuit, comprising:

a main, 1-bit digital-to-analog converter, DAC, configured to receive a 1-bit oversampled digital audio signal, and to output an analog converted version of said digital audio signal;

an offset cancellation block having:

a logic block configured to modulate in frequency modulo 2 P a given P-bit digital offset compensation value, where P is an integer equal to or higher than unity, for outputting a modulated digital offset compensation signal; and,

an auxiliary DAC configured to output an analog converted version of the modulated digital offset compensation signal; and,

an analog mixer configured to combine the analog audio signal from the main DAC with the analog converted version of the modulated digital offset signal, into an offset compensated analog audio signal.

2. The driver circuit of claim 1 , further comprising an analog filter configured to smooth the offset compensated analog audio signal and to provide an analog output signal suitable for driving an audio transducer.

3. The driver circuit of claim 1 , wherein the P-bits offset compensation value is defined based on a measure of a DC voltage at the analog filter output under determined conditions of operation of the driver circuit.

4. The driver circuit of claim 1 , wherein the main DAC and the auxiliary DAC both have a thermometer code based DAC architecture with respective complementary current outputs, followed by a summing and current-to-voltage converting stage.

5. The driver circuit of claim 4 , wherein the analog filter is integral with the summing and current-to-voltage converting stage.

6. The driver circuit of claim 1 , wherein the logic block of the offset cancellation block is adapted to modulate the digital offset value as a function of a clock signal clocking both the main DAC and the auxiliary DAC.

7. The driver circuit of claim 6 , wherein the modulated digital offset signal is the result of a temporal convolution between the clock signal and the digital offset value, providing a modulated digital offset signal average between −2 P and +2 P .

8. The driver circuit of claim 1 , wherein the conversion coefficient of the auxiliary DAC is lower than the conversion coefficient of the main DAC.

9. The driver circuit of claim 8 , wherein the conversion coefficient of the auxiliary digital-to-analog converter is at least three times lower than the conversion coefficient of the main digital-to-analog converter.

10. The driver circuit of claim 1 , wherein an out of band power of the analog converted version of the modulated digital offset value associated to an offset introduced in the auxiliary DAC, is lower than an out-of-band noise provided by the main DAC.

11. The driver circuit of claim 1 , wherein P=5.

12. Audio power amplifier comprising an audio driver circuit according to claim 1 .

13. Integrated Circuit comprising a digital part and an analog part), wherein the analog part comprises the audio power amplifier of claim 12 .

14. Wireless product, comprising the Integrated Circuit of claim 13 .

15. Method of digital-to-analog converting a 1-bit oversampled digital audio signal, comprising:

generating an analog converted version of the 1-bit oversampled digital audio signal using a main, 1-bit digital-to-analog converter;

modulating in frequency modulo 2 P a given P-bit digital offset compensation value, where P is an integer equal to or higher than unity, for generating a modulated digital offset compensation signal;

generating an analog converted version of the modulated digital offset compensation signal using an auxiliary DAC;

combining the analog audio signal from the main DAC with the analog converted version of the modulated digital offset signal, into an offset compensated analog audio signal.

Assignments (2)
STATUS CHANGE-ENTITY IN LIQUIDATION Recorded Feb 2, 2016
From: ST-ERICSSON SA
To: ST-ERICSSON SA, EN LIQUIDATION
Reel/Frame 037739/0493 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 20, 2014
From: FRAISSE, CHRISTIAN; NIGARI, ANGELO
To: ST-ERICSSON SA
Reel/Frame 032001/0769 →
Priority Claims (1)
EP 12306693 · Dec 27, 2012 · regional
Continuity (2)
Provisional Application 61752004 · Jan 14, 2013
Related Publication 20140185835A1 · Jul 3, 2014