IP Library Granted Patent US 9,252,659
Granted Patent B2
US 9,252,659 · App. 14/137,203 · Granted Feb 2, 2016

DC-DC converter with adaptive phase compensation controller

Inventor: Hideta Oki (Kanagawa, JP)
Assignee: CYPRESS SEMICONDUCTOR CORPORATION
H02M3/06H02M3/156H02M3/158
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Quick Facts
Patent No.
US 9,252,659
App. No.
14/137,203
Granted
Feb 2, 2016
Kind
B2
Abstract

A DC-DC converter for generating an output voltage from input voltage, includes: an output stage for outputting the output voltage; an error amplifier having an input and a reference input for receiving a feedback voltage at the input in accordance with the output voltage and for receiving a reference voltage at the reference input, the error amplifier generating an amplified voltage for driving the output stage, the amplifier voltage corresponding to the difference between the feedback voltage and the reference voltage; a phase compensation unit for generating a phase compensation component to the feedback voltage; and a phase compensation controller for controlling the phase of the phase compensation unit; wherein the feedback voltage determined by the output voltage plus said phase compensation component.

Claims (26)

1. A DC-DC converter for generating an output voltage from an input voltage, comprising:

an error amplifier configured to receive a feedback voltage at a first input in accordance with the output voltage, to receive a reference voltage at a second input, and to output an amplified voltage, the amplified voltage corresponding to a difference between the feedback voltage and the reference voltage;

a phase compensation circuit configured to adjust a phase of the feedback voltage, the phase compensation circuit having at least one variable impedance element controlled by a control voltage and coupled to the error amplifier; and

a phase compensation controller configured to generate the control voltage by amplifying a voltage difference between the input voltage and output voltage to control a phase compensation component of the phase compensation circuit.

2. The DC-DC converter of claim 1 , wherein the at least one variable impedance element includes a variable capacitor connected to the first input of the error amplifier.

3. The DC-DC converter of claim 2 , wherein the variable capacitor includes a transistor having a backgate that is coupled to the first input of the error amplifier.

4. The DC-DC converter of claim 3 , wherein a capacitance of the variable capacitor is configured to be small when the control voltage is large, and to be large when the control voltage is small.

5. The DC-DC converter of claim 3 , wherein a gate of the transistor is configured to receive the control voltage.

6. The DC-DC converter of claim 1 , wherein the at least one variable impedance element includes a variable resistor connected to an output of the error amplifier.

7. The DC-DC converter of claim 6 , wherein the variable resistor includes a transistor having a backgate connected to the output of the error amplifier.

8. The DC-DC converter of claim 7 , wherein a gate of the transistor is configured to receive the control voltage.

9. The DC-DC converter of claim 1 , wherein the at least one variable impedance element includes a variable resistor and a variable capacitor.

10. The DC-DC converter of claim 9 , wherein the variable resistor includes a first transistor having a first backgate connected to an output of the error amplifier, and

wherein the variable capacitor includes a second transistor having a second backgate connected to the first input of the error amplifier.

11. The DC-DC converter of claim 10 , wherein the variable resistor includes a source terminal or a drain terminal connected to one of a source terminal or a drain terminal of the variable capacitor.

12. The DC-DC converter of claim 10 , wherein a gate of the first transistor and a gate of the second transistor are each connected to a common node that is configured to receive the control voltage.

13. The DC-DC converter of claim 1 , further comprising an output stage configured to output the output voltage based on the input voltage.

14. The DC-DC converter of claim 13 , wherein the error amplifier is configured to output the amplified voltage to the output stage.

15. The DC-DC converter of claim 2 , further comprising a feedback loop connected between an output of the error amplifier and the first input and configured to provide the first input with the feedback voltage, the feedback loop including the variable capacitor and a resistor connected in series,

wherein the control voltage controls the capacitance of the variable capacitor.

16. The DC-DC converter of claim 6 , further comprising a feedback loop connected between an output of the error amplifier and the first input and configured to provide the first input with the feedback voltage, the feedback loop including the variable resistor and a capacitor connected in series,

wherein the control voltage controls the resistance of the variable resistor.

17. The DC-DC converter of claim 9 , further comprising a feedback loop connected between an output of the error amplifier and the first input and configured to provide the first input with the feedback voltage, the feedback loop including the variable resistor and the variable capacitor connected in series,

wherein the control voltage controls the resistance of the variable resistor and the capacitance of the variable capacitor.

18. The DC-DC converter of claim 7 , wherein the transistor includes a source terminal and a drain terminal, one of the source terminal or the drain terminal being connected to the backgate of the transistor and the output of the error amplifier.

19. The DC-DC converter of claim 9 , wherein the first transistor includes a source terminal and a drain terminal, one of the source terminal or the drain terminal being connected to the backgate of the first transistor and the output of the error amplifier.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Mar 16, 2022
From: MUFG UNION BANK, N.A.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 059410/0438 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Oct 28, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MUFG UNION BANK, N.A.
Reel/Frame 050896/0366 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 1, 2018
From: SPANSION LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 045476/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 10, 2018
From: FUJITSU SEMICONDUCTOR LIMITED
To: SPANSION LLC
Reel/Frame 045034/0700 →
CHANGE OF NAME Recorded Nov 30, 2017
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 044573/0738 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 26, 2017
From: OKI, HIDETA
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 043962/0950 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
Priority Claims (1)
JP 2008-305307 · Nov 28, 2008 · national
Continuity (2)
Continuation 12617427 · Nov 12, 2009
Related Publication 20140306752A1 · Oct 16, 2014