Method for forming dual oxide trench gate power MOSFET using oxide filled trench

1. A method for forming a dual oxide thickness trench gate structure including a termination structure for a power MOSFET, comprising:

providing a semiconductor substrate;

forming a hard mask layer on the semiconductor substrate;

forming a first dielectric cap layer on the hard mask layer;

patterning the hard mask layer and the first dielectric cap layer to define a first trench being an active trench and a second trench being a termination trench, the second trench being formed along an edge of the semiconductor substrate to form the termination structure;

forming, using the hard mask layer and the first dielectric cap layer as a mask, the first trench and the second trench on a top surface of the substrate, the second trench having a width wider than a width of the first trench and having a depth deeper than a depth of the first trench;

forming a first oxide layer on the semiconductor substrate and filling the first trench and the second trench, the first oxide layer being formed on the patterned first dielectric cap layer and the hard mask layer;

forming a second dielectric cap layer on the first oxide layer;

patterning the second dielectric cap layer to define areas for forming the trench gate structure comprising patterning the second dielectric cap layer to expose at least areas including an entire opening of the first trench and an inner portion of an opening of the second trench away from the edge of the semiconductor substrate, an outer portion of the opening of the second trench being covered by the second dielectric cap layer;

etching, using the second dielectric cap layer as a mask, a portion of the first oxide layer in the first trench and the second trench, the first oxide layer being removed from a top portion of the first trench and remaining only in a bottom portion of the first trench, the bottom portion of the first oxide layer in the first trench having a first depth from a bottom of the first trench, and the first oxide layer being removed from a top portion of the inner portion of the second trench and remaining in a bottom portion of the second trench and an outer sidewall portion of the second trench forming a sidewall oxide portion, the sidewall oxide portion being masked from etching by the second dielectric cap layer and lining an outer edge of an entire depth of the second trench;

forming dielectric spacers along sidewalls of the first trench and the second trench and on the first oxide layer formed in the respective first and second trenches, the dielectric spacers being formed on the sidewall oxide portion in the second trench;

etching, using the dielectric spacers as a mask, the first oxide layer in the first trench and the second trench to a second depth from the bottom of the first trench, the second depth being lower than the first depth;

removing the dielectric spacers; and

forming a second oxide layer along the sidewall of the first trench above the first oxide layer and at least along the sidewall of an inner edge of the second trench, the second oxide layer having a thickness thinner than a thickness of the first oxide layer.

2. The method of claim 1 , further comprising:

forming a polysilicon layer in the first trench and the second trench, the polysilicon layer forming a trench gate of the power MOSFET in the first trench and in the inner edge of the second trench, the second oxide layer comprising a gate oxide layer and the first oxide layer comprising a liner oxide layer.

3. The method of claim 2 , wherein forming a first oxide layer on the semiconductor substrate and filling the first trench and the second trench comprises depositing the first oxide layer on the semiconductor substrate and in the first and second trenches; and forming a second oxide layer along the sidewall of the first trench above the first oxide layer and at least along the sidewall of an inner edge of the second trench comprises performing thermal oxidation to form the second oxide layer along the sidewall of the first trench above the first oxide layer and at least along the sidewall of the inner edge of the second trench.

4. The method of claim 3 , wherein depositing the first oxide layer on the semiconductor substrate and in the first and second trenches comprises depositing a high density plasma oxide layer on the semiconductor substrate and in the first and second trenches.

5. The method of claim 1 , wherein forming a hard mask layer on the semiconductor substrate comprises forming a silicon nitride layer sandwiched between two silicon oxide layers as the hard mask layer; and forming a first dielectric cap layer on the hard mask layer comprises forming a first silicon nitride cap layer on the hard mask layer.

6. The method of claim 1 , wherein forming a second dielectric cap layer on the first oxide layer comprises forming a second silicon nitride cap layer on the first oxide layer.

7. The method of claim 1 wherein forming dielectric spacers along the sidewalls of the first trench and the second trench and on the first oxide layer comprises:

forming silicon nitride spacers along the sidewalls of the first trench and the second trench and on the first oxide layer.

8. The method of claim 2 , further comprising:

forming a body region in the silicon substrate adjacent to the first trench and the inner edge of the second trench;

forming a source region in the body region; and

forming a contact to the body region and the source region.