Methods of fabricating semiconductor devices and semiconductor devices fabricated thereby

1. A method of fabricating a semiconductor device, the method comprising:

forming an array of pillars over an underlying layer;

forming a separation wall layer over the pillars and the underlying layer;

forming a block co-polymer (BCP) layer over the separation wall layer to fill gaps between the pillars; and

phase-separating the BCP layer into first and second domains,

wherein the first domains include second separation walls formed over sidewalls of the first separation wall layer, and

wherein the second domains are separated from the pillars by the first domains.

2. The method of claim 1 , further comprising:

selectively removing the second domains to form first openings; and

selectively removing the pillars to form second openings.

3. The method of claim 2 , further comprising:

etching the separation wall layer to expose top surfaces of the pillars; and

etching the separation wall layer exposed by the first openings, before forming the second openings.

4. The method of claim 2 , further comprising:

selectively etching the underlying layer exposed by the first and second openings to form a mask pattern.

5. The method of claim 4 , further comprising:

sequentially forming an etch target layer and a hard mask layer over a semiconductor substrate before forming the underlying layer over the semiconductor substrate;

etching the hard mask layer using the mask pattern as an etch mask to form a hard mask;

etching the etch target layer using the hard mask as an etch mask to form contact holes; and

forming conductive electrodes in the contact holes.

6. The method of claim 5 , wherein the conductive electrodes includes (i) storage node contacts or storage nodes of cell capacitors of a dynamic random access memory (DRAM) device or (ii) lower electrodes contacting variable resistive layers of a resistive random access memory (ReRAM) device.

7. The method of claim 5 ,

wherein the hard mask layer includes a carbon layer; and

wherein the underlying layer includes a silicon oxynitride (SiON) layer or a combination layer of a silicon oxynitride (SiON) layer and a silicon oxide layer.

8. The method of claim 1 , wherein the BCP layer includes a polystyrene-poly(methyl meta acrylate) (PS-PMMA) co-polymer material or a silicon-contained polystyrene-poly(di methyl siloxane) (Si contained PS-PDMS) co-polymer material.

9. The method of claim 1 , wherein the BCP layer is formed to expose top surfaces of the pillars.

10. The method of claim 1 ,

wherein a unit array of the pillars includes three pillars located at three vertex of a triangle or four pillars located at four vertex of a tetragon; and

wherein each of the second domains is formed at a central region of the triangle or the tetragon.

11. The method of claim 10 ,

wherein each of the first domains fills a gap between two adjacent pillars arranged in a row direction;

wherein each of the first domains defines a recessed region in the central region of the triangle or the tetragon; and

wherein each of the second domains fills the recessed region.

12. A method of fabricating a semiconductor device, the method comprising:

forming an array of pillars over an underlying layer;

forming first separation walls over sidewalls of the pillars;

forming a block co-polymer (BCP) layer filling gaps between the pillars; and

phase-separating the BCP layer into first and second domains,

wherein the first domains include second separation walls formed over the first separation walls, and

wherein the second domains are separated from the pillars by the first domains.

13. The method of claim 12 , wherein forming the first separation walls includes:

forming a separation wall layer covering the pillars and the underlying layer; and

anisotropically etching the separation wall layer to expose top surfaces of the pillars and the underlying layer between the pillars.

14. The method of claim 12 , further comprising:

selectively removing the second domains to form first openings; and

selectively removing the pillars to form second openings.

15. The method of claim 12 , wherein the BCP layer is formed over the underlying layer exposed by the first separation walls.

16. The method of claim 12 ,

wherein a unit array of the pillars includes three pillars located at three vertex of a triangle or four pillars located at four vertex of a tetragon; and

wherein the second domains are formed at central regions of the triangles or the tetragons and on top surfaces of the pillars.

17. The method of claim 16 ,

wherein each of the first domains is formed to fill a gap between two adjacent pillars arranged in a row direction;

wherein each of the first domains defines a recessed region in the central region of the triangle or the tetragon; and

wherein each of the second domains fills the recessed region.

18. A method of fabricating a semiconductor device, the method comprising:

forming an array of first separation walls over an underlying layer, each of the first separation walls having a hollow cylindrical shape;

forming a block co-polymer (BCP) layer filling inside regions of the first separation walls and gaps between the first separation walls; and

phase-separating the BCP layer into first and second domains,

wherein the first domains includes second separation walls formed over inner sidewalls and outer sidewalls of the first separation walls, and

wherein the second domains are separated from each other by the first domains.

19. The method of claim 18 , wherein forming the array of the first separation walls includes:

forming an array of pillars over the underlying layer;

forming a separation wall layer over the pillars and the underlying layer;

anisotropically etching the separation wall layer to form the first separation walls over sidewalls of the pillars; and

selectively removing the pillars.

20. The method of claim 18 , further comprising:

selectively removing the second domains to form openings in inside regions and outside regions of the first separation walls.