Semiconductor Structure Including A Spatially Confined Dielectric Region
There are disclosed herein various implementations of semiconductor structures including one or more spatially confined dielectric regions. In one exemplary implementation, such a semiconductor structure includes a III-Nitride field-effect transistor (FET) having a drain, a source, and a gate, fabricated over a substrate. A spatially confined dielectric region is formed under the drain in the substrate, the spatially confined dielectric region reducing a capacitive coupling of the drain to the substrate. In another exemplary implementation, a spatially confined dielectric region is formed under each of the source and the drain of the FET, in the substrate, the spatially confined dielectric regions reducing a capacitive coupling of the source and the drain to the substrate.
1 . A semiconductor structure comprising:
a III-Nitride field-effect transistor (FET) including a drain, a source, and a gate, fabricated over a substrate;
a spatially confined dielectric region formed under said drain in said substrate;
said spatially confined dielectric region reducing a capacitive coupling of said drain to said substrate.
2 . The semiconductor structure of claim 1 , wherein said spatially confined dielectric region is substantially centered under said drain.
3 . The semiconductor structure of claim 1 , wherein said spatially confined dielectric region comprises silicon oxide.
4 . The semiconductor structure of claim 1 , wherein said substrate comprises a group IV semiconductor substrate.
5 . The semiconductor structure of claim 1 , wherein said substrate is one of a silicon substrate and a composite silicon substrate.
6 . The semiconductor structure of claim 1 , wherein said III-Nitride FET comprises a III-Nitride high electron mobility transistor (HEMT).
7 . A semiconductor structure comprising:
a III-Nitride field-effect transistor (FET) including a drain, a source, and a gate, fabricated over a substrate;
a spatially confined dielectric region formed under each of said source and said drain in said substrate;
said spatially confined dielectric region reducing a capacitive coupling of said source and said drain to said substrate.
8 . The semiconductor structure of claim 7 , wherein all sides of said spatially confined dielectric region are surrounded by said substrate.
9 . The semiconductor structure of claim 7 , wherein a top side of said spatially confined dielectric region is not covered by said substrate.
10 . A method comprising:
forming a spatially confined dielectric region in a substrate;
fabricating a III-Nitride field-effect transistor (FET) over said substrate, said III-Nitride FET including a drain, a source, and a gate;
said drain of said III-Nitride FET being formed over said spatially confined dielectric region so as to reduce a capacitive coupling of said drain to said substrate.
11 . The method of claim 10 , wherein said spatially confined dielectric region is formed through oxygen implantation of said substrate.
12 . The method of claim 10 , further comprising forming a silicon lateral epitaxial overgrowth layer above said spatially confined dielectric region and below said III-Nitride FET.
13 . The method of claim 10 , wherein said spatially confined dielectric region is substantially centered under said drain.
14 . The method of claim 10 , wherein said substrate comprises a group IV semiconductor substrate.
15 . The method of claim 10 , wherein said substrate is one of a silicon substrate and a composite silicon substrate.
16 . A method comprising:
forming spatially confined dielectric regions in a substrate;
fabricating a III-Nitride field-effect transistor (FET) over said substrate, said III-Nitride FET including a drain, a source, and a gate;
each of said drain and said source of said III-Nitride FET being formed over a respective one of said spatially confined dielectric regions so as to reduce a capacitive coupling of said drain and said source to said substrate.
17 . The method of claim 16 , wherein said spatially confined dielectric regions are formed through oxygen implantation of said substrate.
18 . The method of claim 16 , further comprising forming a silicon lateral epitaxial overgrowth layer above said spatially confined dielectric regions and below said III-Nitride FET.
19 . The method of claim 16 , wherein said substrate comprises a group IV semiconductor substrate.
20 . The method of claim 16 , wherein said substrate is one of a silicon substrate and a composite silicon substrate.