Source/drain structure of semiconductor device

1. A fin field effect transistor (FinFET) comprising:

an isolation structure comprising a top surface over a substrate major surface;

a cavity having a convex bottom surface below the top surface;

a strained material in the cavity and extending above the top surface, wherein the strained material comprises an upper portion having a rhombus shape and a lower portion having substantially vertical sidewalls; and

a pair of tapered spacers adjoining a portion of the substantially vertical sidewalls above the top surface.

2. The FinFET of claim 1 , wherein the strained material comprises SiGe, SiC, or SiP.

3. The FinFET of claim 1 , wherein the lower portion has a bottom surface along the convex bottom surface connecting the substantially vertical sidewalls.

4. The FinFET of claim 1 , wherein the pair of tapered spacers comprises a dielectric layer.

5. The FinFET of claim 4 , wherein the dielectric layer comprises silicon oxide, silicon nitride, or silicon oxy-nitride.

6. The FinFET of claim 1 , wherein a second height of the upper portion is greater than a first height of the pair of tapered spacers.

7. The FinFET of claim 6 , wherein a ratio of the second height to the first height is from 1.5 to 3.5.

8. A fin field effect transistor (FinFET) comprising:

a substrate comprising a major surface;

a fin structure protruding from the major surface;

an isolation structure surrounding the fin structure, wherein a top surface of the isolation structure is over the major surface;

a cavity having a convex bottom surface below the top surface and along a concave top surface of the fin structure;

a strained material in the cavity and extending above the top surface, wherein the strained material comprises an upper portion having a rhombus shape and a lower portion having substantially vertical sidewalls; and

a pair of tapered spacers adjoining a portion of the substantially vertical sidewalls above the top surface.

9. The FinFET of claim 8 , wherein the strained material comprises SiGe, SiC, or SiP.

10. The FinFET of claim 8 , wherein the lower portion has a bottom surface along the convex bottom surface connecting the substantially vertical sidewalls.

11. The FinFET of claim 8 , wherein the pair of tapered spacers comprises a dielectric layer.

12. The FinFET of claim 11 , wherein the dielectric layer comprises silicon oxide, silicon nitride, or silicon oxy-nitride.

13. The FinFET of claim 8 , wherein a second height of the upper portion is greater than a first height of the pair of tapered spacers.

14. The FinFET of claim 13 , wherein a ratio of the second height to the first height is from 1.5 to 3.5.

15. A method of fabricating a fin field effect transistor (FinFET), the method comprising:

providing a substrate having an isolation structure surrounding a semiconductor fin, wherein a top surface of the isolation structure is below a fin top surface of the semiconductor fin;

removing a portion of the semiconductor fin to form a concave top surface of a remaining semiconductor fin;

forming a dielectric layer over the remaining semiconductor fin and extending over the isolation structure;

removing a portion of the dielectric layer to expose the concave top surface of the remaining semiconductor fin, whereby a remaining dielectric layer on sidewall surfaces of the remaining semiconductor fin forms a pair of tapered spacers;

recessing a portion of the remaining semiconductor fin to form a cavity having a convex bottom surface below the top surface; and

epi-growing a strained material in the cavity and extending above the top surface, wherein the strained material comprises an upper portion having a rhombus shape and a lower portion having substantially vertical sidewalls.

16. The method of claim 15 , wherein removing a portion of the dielectric layer to expose the concave top surface of the remaining semiconductor fin is performed under a power of about 200 Watt to about 600 Watt.

17. The method of claim 15 , wherein removing a portion of the dielectric layer to expose the concave top surface of the remaining semiconductor fin is performed under a pressure of about 2 mTorr to about 20 mTorr.

18. The method of claim 15 , wherein recessing a portion of the remaining semiconductor fin to form a cavity having a convex bottom surface below the top surface is performed under a power of about 200 Watt to about 600 Watt.

19. The method of claim 15 , wherein recessing a portion of the remaining semiconductor fin to form a cavity having a convex bottom surface below the top surface is performed under a pressure of about 2 mTorr to about 20 mTorr.

20. The method of claim 15 , wherein recessing a portion of the remaining semiconductor fin to form a cavity having a convex bottom surface below the top surface is performed using HBr and O 2 as reaction gases.