Electronic device comprising a semiconductor memory unit
Devices and methods based on disclosed technology include, among others, an electronic device capable of improving a signal transfer characteristic and a method for fabricating the same. Specifically, an electronic device in one implementation includes a plurality of buried gates formed in a substrate, open parts formed in the substrate on both sides of the buried gate, isolation layers each formed between a sidewall of the open part and a sidewall of the buried gate, source/drain regions formed in the substrate under the respective open parts, and contact plugs buried in the respective open parts.
1. An electronic device comprising a semiconductor memory unit that includes:
a substrate;
word lines including a plurality of buried gates formed in the substrate;
open parts formed in the substrate on two opposing sides of the buried gates;
isolation layers formed in the open parts, each isolation layer formed between a sidewall of an open part and a sidewall of a corresponding buried gate;
source and drain regions formed in the substrate under respective open parts;
contact plugs buried in respective open parts;
a source line coupled with the source regions;
variable resistance elements coupled with respective drain regions; and
bit lines coupled with respective variable resistance elements.
2. The electronic device of claim 1 , further comprising ohmic contact layers formed in the source and drain regions and exposed to the open parts.
3. The electronic device of claim 1 , wherein each of the buried gates comprises:
a trench formed in the substrate;
a gate insulating layer formed on a surface of the trench;
a gate electrode formed over the gate insulating layer and configured to bury part of the trench; and
a sealing layer formed over the gate electrode and configured to bury the remaining trench.
4. The electronic device of claim 3 , wherein a bottom of the open part is lower than an interface where the gate electrode comes in contact with the sealing layer.
5. The electronic device of claim 4 , wherein the isolation layer comprises an insulating layer.
6. The electronic device of claim 4 , wherein the open parts comprise:
first open parts formed in the substrate on both sides of the buried gate and each configured to have a first critical dimension; and
second open parts formed under the first open parts and each configured to have a second critical dimension smaller than the first critical dimension.
7. The electronic device of claim 6 , wherein the isolation layer comprises a substrate remaining between a sidewall of the second open part and a sidewall of the buried gate.
8. The electronic device of claim 1 , wherein each of the contact plugs comprises a metallic layer.
9. The electronic device of claim 1 , wherein each of the variable resistance elements comprises a stack layer having a tunnel barrier layer interposed between two magnetic material layers.
10. The electronic device of claim 1 , wherein each of the variable resistance elements comprises metal oxide.
11. The electronic device of claim 1 , wherein each of the variable resistance elements comprises phase-change materials.
12. The electronic device according to claim 1 , further comprising a microprocessor which includes:
a control unit configured to receive a signal including a command from an outside of the microprocessor, and performs extracting, decoding of the command, or controlling input or output of a signal of the microprocessor;
an operation unit configured to perform an operation based on a result that the control unit decodes the command; and
a memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed,
wherein the semiconductor memory unit is part of the memory unit in the microprocessor.
13. An electronic device comprising a semiconductor circuit that includes:
a substrate;
trenches formed in the substrate;
conductors located inside the trenches, respectively, to form gate electrodes buried inside the trenches;
source and drain regions formed in the substrate and adjacent to the trenches;
open parts formed above the source and drain regions on opposing sides of each of the gate electrodes buried inside respective trenches;
isolation layers formed inside the open parts and above respective source and drain regions, each isolation layer formed between a sidewall of an open part and a sidewall of a gate electrode; and
contact plugs buried inside the open parts to provide electrical contacts with the source and drain regions, respectively, wherein a gate electrode buried in side a trench and adjacent source and drain regions form a transistor.
14. The device of claim 13 , wherein:
the semiconductor circuit includes a circuit element that is electrically coupled to a contact plug buried inside a respective open part of a transistor.
15. The device of claim 14 , wherein:
the circuit element includes a semiconductor memory.
16. The device of claim 15 , wherein:
the semiconductor memory includes a variable resistance layer that changes a resistance value to represent stored data.
17. The device of claim 15 , wherein:
the semiconductor memory includes a phase-change material.
18. The device of claim 15 , wherein:
the semiconductor memory includes a magnetic tunnel junction.
19. The device of claim 14 , wherein:
the substrate includes active regions each having one or more of the trenches and isolation layers each formed between two active regions to isolate the two active regions.
20. The device of claim 19 , wherein:
one or more of the trenches are formed in the isolation layers.