IP Library › Granted Patent US 9,413,266
Granted Patent B2
US 9,413,266 · App. 14/149,938 · Granted Aug 9, 2016

Power supply with DC breaker switch and reduced regulated DC link voltage

Inventor: Yigang (Jason) Guo (Cupertino, CA)
Assignee: Fairchild Semiconductor Corporation
H02M7/2176
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Quick Facts
Patent No.
US 9,413,266
App. No.
14/149,938
Granted
Aug 9, 2016
Kind
B2
Abstract

Generally, this disclosure provides circuits and methods to reduce and regulate DC link voltage in a power supply through the use of a DC breaker circuit. The breaker circuit may include a breaker switch configured to couple an input stage circuit of a power supply to an output stage circuit of the power supply and to provide a regulated DC link voltage to the output stage circuit, the level of the DC link voltage based on switching states of the breaker switch. The breaker circuit may further include a control circuit configured to generate a gate control signal to control the switching states of the breaker switch, the gate control signal based on a comparison of the DC link voltage to a high voltage threshold and a low voltage threshold, such that the magnitude of the DC link voltage is regulated to a set point and a peak-to-peak ripple.

Claims (25)

1. A direct current (DC) breaker circuit comprising:

a breaker switch configured to couple an input stage circuit of a power supply to an output stage circuit of said power supply and to provide a regulated DC link voltage to said output stage circuit, the level of said DC link voltage based on switching states of said breaker switch;

a control circuit configured to generate a gate control signal to control said switching states of said breaker switch, said gate control signal based on a comparison of said DC link voltage to a high voltage threshold and a low voltage threshold, such that the magnitude of said DC link voltage is regulated to a set point and a peak-to-peak ripple; and

said control circuit further configured to generate said gate control signal such that said breaker switch state changes are synchronized with a frequency of a voltage provided by said input stage circuit to provide a zero voltage switching (ZVS) condition of said breaker switch.

2. The DC breaker circuit of claim 1 , further comprising a hysteresis control circuit configured to limit switching state changes of said breaker circuit in response to noise associated with said voltage provided by said input stage circuit.

3. The DC breaker circuit of claim 1 , wherein said breaker switch is a synchronous bridge rectifier.

4. The DC breaker circuit of claim 1 , wherein said breaker switch is a bridgeless rectifier.

5. A method for reducing and regulating a DC link voltage in a power supply, said method comprising:

coupling an input stage circuit of a power supply to an output stage circuit of said power supply with a breaker switch;

configuring said breaker switch to provide a DC link voltage to said output stage circuit, the level of said DC link voltage based on switching states of said breaker switch;

generating a gate control signal to control said switching states of said breaker switch, said gate control signal based on a comparison of said DC link voltage to a high voltage threshold and a low voltage threshold, such that the magnitude of said DC link voltage is regulated to a set point and a peak-to-peak ripple; and

timing said gate control signal such that said breaker switch state changes provide a zero voltage switching (ZVS) condition of said breaker switch.

6. The method of claim 5 , wherein said breaker switch is a bridgeless rectifier.

7. The method of claim 5 , wherein said breaker switch is a synchronous bridge rectifier.

8. The method of claim 5 , further comprising limiting switching state changes of said breaker switch in response to noise associated with said voltage provided by said input stage circuit.

9. A power supply system comprising:

an input stage circuit configured to accept an input voltage;

an output stage circuit configured to provide an output voltage;

a breaker switch configured to couple said input stage circuit to said output stage circuit and to provide a regulated DC link voltage to said output stage circuit, the level of said DC link voltage based on switching states of said breaker switch; and

a control circuit configured to generate a gate control signal to control said switching states of said breaker switch, said gate control signal based on a comparison of said DC link voltage to a high voltage threshold and a low voltage threshold, such that the magnitude of said DC link voltage is regulated to a set point and a peak-to-peak ripple.

10. The power supply system of claim 9 , wherein said power supply is a switched mode power supply and said input stage circuit comprises an electromagnetic interference (EMI) filter.

11. The power supply system of claim 9 , wherein said breaker switch is a bridgeless rectifier.

12. The power supply system of claim 9 , wherein said breaker switch is a synchronous bridge rectifier.

13. The power supply system of claim 9 , further comprising a hysteresis control circuit configured to limit switching state changes of said breaker switch in response to noise associated with said voltage provided by said input stage circuit.

14. The power supply system of claim 9 , wherein said control circuit is further configured to generate said gate control signal such that said breaker switch state changes are synchronized with a frequency of a voltage provided by said input stage circuit to provide a zero voltage switching (ZVS) condition of said breaker switch.

Assignments (7)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 058871, FRAME 0799 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 065653/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 040075, FRAME 0644 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0536 →
SECURITY INTEREST Recorded Nov 12, 2021
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 058871/0799 →
RELEASE OF SECURITY INTEREST Recorded Oct 28, 2021
From: DEUTSCHE BANK AG NEW YORK BRANCH
To: FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 057969/0206 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 3, 2021
From: FAIRCHILD SEMICONDUCTOR CORPORATION
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 057694/0374 →
PATENT SECURITY AGREEMENT Recorded Sep 19, 2016
From: FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 040075/0644 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 8, 2014
From: GUO, YIGANG (JASON)
To: FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 031914/0840 →
Continuity (2)
Provisional Application 61751438 · Jan 11, 2013
Related Publication 20140198543A1 · Jul 17, 2014