Resistor thin film MTP memory
View Patent ↗An integrated circuit is formed having an array of memory cells located in the dielectric stack above a semiconductor substrate. Each memory cell has two adjustable resistors and two heating elements. A dielectric material separates the heating elements from the adjustable resistors. One heating element alters the resistance of one of the resistors by applying heat thereto to write data to the memory cell. The other heating element alters the resistance of the other resistor by applying heat thereto to erase data from the memory cell.
1. An Integrated circuit die comprising:
a memory cell including:
a first thin film adjustable resistor;
a second thin film adjustable resistor; and
a data writing circuit coupled to the memory cell and configured to write data to the memory cell by altering the resistance of the first thin film adjustable resistor and to erase data from the memory cell by altering the resistance of the second thin film adjustable resistor.
2. The integrated circuit die of claim 1 wherein the memory cell further includes:
a first thin film heating element coupled to the data writing circuit and configured to alter the resistance of the first thin film adjustable resistor by heating the first thin film adjustable resistor; and
a first thin film heating element coupled to the data writing circuit and configured to alter the resistance of the second thin film adjustable resistor by heating the second thin film adjustable resistor.
3. The integrated circuit die of claim 2 wherein the memory cell further includes a dielectric layer a dielectric layer separating the first thin film heating element from the first thin film adjustable resistor and separating the second thin film heating element from the second thin film adjustable resistor.
4. The integrated circuit die of claim 1 wherein the data writing circuit is configured to write data to the memory cell by increasing a difference between the resistances of the first and second thin film adjustable resistors and to erase data from the memory cell by decreasing a difference between the resistances of the first and second thin film adjustable resistors.
5. The integrated circuit die of claim 4 wherein the data writing circuit is configured to erase data from the memory cell by altering the resistance of the second thin film adjustable resistor to be substantially equal to the resistance of the first thin film adjustable resistor.
6. The integrated circuit die of claim 1 wherein the data writing circuit is configured to erase data from the memory cell by increasing a difference between the resistances of the first and second thin film adjustable resistors and to write data from the memory cell by decreasing a difference between the resistances of the first and second thin film adjustable resistors.