IP Library Granted Patent US 9,236,243
Granted Patent B2
US 9,236,243 · App. 14/151,188 · Granted Jan 12, 2016

Method for making semiconductor devices including reactant treatment of residual surface portion

Inventor: ChongJieh Chew (Singapore, SG)
Assignee: STMICROELECTRONICS PTE LTD
H01L21/02252H01L21/0234H01L21/02129H01L21/02321H01L21/033
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Quick Facts
Patent No.
US 9,236,243
App. No.
14/151,188
Granted
Jan 12, 2016
Kind
B2
Abstract

A method for making semiconductor devices may include forming a phosphosilicate glass (PSG) layer on a semiconductor wafer, with the PSG layer having a phosphine residual surface portion. The method may further include exposing the phosphine residual surface portion to a reactant plasma to integrate at least some of the phosphine residual surface portion into the PSG layer. The method may additionally include forming a mask layer on the PSG layer after the exposing.

Claims (20)

1. A method for making semiconductor devices comprising:

forming a phosphosilicate glass (PSG) layer on a semiconductor wafer, the PSG layer having a phosphine residual surface portion on an upper surface of the PSG layer opposite the semiconductor wafer;

exposing the phosphine residual surface portion to a reactant plasma to integrate at least some of the phosphine residual surface portion from the upper surface into the PSG layer; and

forming a mask layer on the PSG layer after the exposing.

2. The method according to claim 1 wherein the reactant plasma comprises oxygen.

3. The method according to claim 1 wherein the forming of the mask layer is performed after the exposing without an intervening scrubbing operation.

4. The method according to claim 1 wherein forming the PSG layer comprises deposition at a first radio frequency (RF) power; and wherein exposing the phosphine residual surface portion to the reactant plasma is at a second RF power less than the first RF power.

5. The method according to claim 1 wherein forming the PSG layer and exposing the phosphine residual surface portion are performed in a radio frequency (RF) plasma chamber.

6. The method according to claim 1 wherein forming the PSG layer and exposing the phosphine residual surface portion are performed at a pressure in a range of 3 to 5 Torr.

7. The method according to claim 1 wherein forming the PSG layer and exposing the phosphine residual surface portion are performed at a temperature in a range of 300 to 500° C.

8. The method according to claim 1 wherein forming the PSG layer and exposing the phosphine residual surface portion are performed with an N 2 O flow rate in a range of 1000-1200 scc.

9. A method for making semiconductor devices comprising:

forming a phosphosilicate glass (PSG) layer on a semiconductor wafer within a radio frequency (RF) plasma processing chamber, the PSG layer having a phosphine residual surface portion on an upper surface of the PSG layer opposite the semiconductor wafer;

exposing the phosphine residual surface portion to a reactant plasma within the RF plasma processing chamber; and

forming a mask layer on the PSG layer after the exposing and without an intervening scrubbing operation.

10. The method according to claim 9 wherein the reactant plasma comprises oxygen.

11. The method according to claim 9 wherein forming the PSG layer comprises deposition at a first radio frequency (RF) power; and wherein exposing the phosphine residual surface portion to the reactant plasma is at a second RF power less than the first RF power.

12. The method according to claim 9 wherein exposing of the phosphine residual surface portion is performed at a pressure in a range of 3 to 5 Torr.

13. The method according to claim 9 wherein forming the PSG layer and exposing the phosphine residual surface portion are performed at a temperature in a range of 300 to 500° C.

14. The method according to claim 9 wherein forming the PSG layer and exposing the phosphine residual surface portion are performed with an N 2 O flow rate in a range of 1000-1200 scc.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 1, 2022
From: STMICROELECTRONICS PTE LTD
To: STMICROELECTRONICS INTERNATIONAL N.V.
Reel/Frame 061608/0496 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 13, 2014
From: CHEW, CHONG JIEH
To: STMICROELECTRONICS PTE LTD
Reel/Frame 031949/0308 →
Continuity (1)
Related Publication 20150194303A1 · Jul 9, 2015