IP Library Granted Patent US 9,911,696
Granted Patent B2
US 9,911,696 · App. 14/152,622 · Granted Mar 6, 2018

Packaged semiconductor assemblies and methods for manufacturing such assemblies

Inventors: Suan Jeung Boon (Singapore, SG); Meow Koon Eng (Singapore, SG); Yong Poo Chia (Singapore, SG)
Assignee: Micron Technology, Inc.
H01L23/5283H01L21/4853H01L21/76885H01L21/82H01L23/49811H01L23/49816H01L23/49827H01L23/522H01L24/19H01L24/48H01L24/81H01L24/82H01L24/85H01L24/97H01L25/03H01L25/0657H01L25/105H01L25/50H01L24/45H01L2224/04105H01L2224/12105H01L2224/32145H01L2224/32225H01L2224/45015H01L2224/4554H01L2224/45124H01L2224/45139H01L2224/45144H01L2224/45147H01L2224/45155H01L2224/45169H01L2224/45669H01L2224/48095H01L2224/48145H01L2224/48464H01L2224/48599H01L2224/48699H01L2224/73267H01L2224/85205H01L2224/85909H01L2224/97H01L2225/06506H01L2225/06524H01L2225/06527H01L2225/06541H01L2225/1023H01L2225/1035H01L2225/1052H01L2225/1058H01L2225/1064H01L2924/00014H01L2924/014H01L2924/01014H01L2924/01022H01L2924/01028H01L2924/01029H01L2924/01033H01L2924/01047H01L2924/01074H01L2924/01078H01L2924/01079H01L2924/01082H01L2924/10253H01L2924/12042H01L2924/14H01L2924/15311H01L2924/15331H01L2924/18162H01L2924/19107
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Quick Facts
Patent No.
US 9,911,696
App. No.
14/152,622
Granted
Mar 6, 2018
Kind
B2
Abstract

Packaged semiconductor assemblies including interconnect structures and methods for forming such interconnect structures are disclosed herein. One embodiment of a packaged semiconductor assembly includes a support member having a first bond-site and a die carried by the support member having a second bond-site. An interconnect structure is connected between the first and second bond-sites and includes a wire that is coupled to at least one of the first and second bond-sites. The interconnect structure also includes a third bond-site coupled to the wire between the first and second bond-sites.

Claims (26)

1. A stacked semiconductor assembly, comprising:

a first package including a first die and a first die redistribution structure attached to the first die, wherein the first die redistribution structure includes a first bond-site electrically connected directly to the first die via the first die redistribution structure, wherein the first die redistribution structure has a first footprint, and wherein the first bond-site has a first width, a first surface and an inner edge;

a second package carried by the first package and including a second die generally identical to the first die, and a second die redistribution structure attached to the second die, wherein the second die redistribution structure includes a second bond-site electrically connected directly to the second die via the second die redistribution structure, wherein the second die redistribution structure has a second footprint smaller than the first footprint, and wherein the second bond-site has a second width smaller than the first width and an inner edge aligned with the inner edge of the first bond-site along an axis normal to the first surface of the first bond-site;

an interconnect structure connected between the first and second bond-sites; and

an encapsulant disposed at least partially around the interconnect structure and the first and second bond-sites, wherein a portion of the second die redistribution structure is accessible through an opening in the encapsulant.

2. The assembly of claim 1 wherein the first package carries the second package with the first bond-site overlapping the second bond-site.

3. The assembly of claim 1 wherein the first and second bond-sites each include an outer edge, and wherein the outer edge of the first bond-site is laterally offset from the outer edge of the second bond-site.

4. The assembly of claim 1 wherein the interconnect structure includes a wire bond attached directly to the first and second bond-sites.

5. The assembly of claim 1 wherein the interconnect structure includes a conductive ink disposed between the first and second bond-sites.

6. The assembly of claim 1 wherein the second die redistribution structure further comprises a third bond-site at an exterior surface of the second package, wherein the third bond-site is coupled to the interconnect structure.

7. The assembly of claim 6 wherein the second bond-site is covered by the encapsulant.

8. The assembly of claim 1 wherein the first die redistribution structure includes a third bond-site, and wherein the assembly further comprises an adhesive covering the third bond-site and attaching the first and second packages to one other.

9. The assembly of claim 1 wherein the encapsulant is a first encapsulant, the first package includes a second encapsulant disposed at least partially around the first die, and the second encapsulant is separated from the first encapsulant by the first die redistribution structure.

10. The assembly of claim 9 wherein the second package includes a third encapsulant disposed at least partially around the second die, and wherein a portion of the first encapsulant is between the third encapsulant and the first die redistribution structure.

11. A stacked semiconductor assembly, comprising:

a first package having a first footprint, and including a first die and a first die redistribution structure electrically connected to the first die, wherein the first die redistribution structure includes a first bond-site having a first surface and electrically connected directly to the first die via the first die redistribution structure;

a first encapsulant partially encapsulating the first package, wherein a portion of the first package is exposed through the first encapsulant;

a second package carrying the first package and having a second footprint that is larger than the first footprint, the second package including a second die, a second die redistribution structure electrically connected to the second die, and a second encapsulant at least partially encapsulating the second die, wherein the second encapsulant is separated from the first encapsulant by the second die redistribution structure and the second die redistribution structure includes a second bond-site electrically connected directly to the second die via the second die redistribution structure, wherein the first and second bond-sites each include inner edges that are aligned with one another along an axis normal to the first surface of the first bond-site, and wherein the first bond-site extends from the axis by a first width and the second bond-site extends from the axis by a second width greater than the first width; and

an interconnect structure connected between the first and second bond-sites and at least partially encapsulated by the first encapsulant, wherein the second bond-site is connected to the interconnect structure.

12. The assembly of claim 11 wherein the first die redistribution structure includes a third bond-site coupled to the first bond-site, wherein the third bond-site is accessible through the first encapsulant.

13. The assembly of claim 12 wherein the second die redistribution structure includes a fourth bond-site coupled to the second bond-site, the assembly further comprises an adhesive material attaching the first package to the second package, and the fourth bond-site is covered by the adhesive.

14. The assembly of claim 12 wherein the first bond-site is covered by the first encapsulant.

15. The assembly of claim 11 wherein first package further includes a third encapsulant at least partially encapsulating the first die, and wherein a portion of the first encapsulant is between the third encapsulant and the second die redistribution structure.

16. The assembly of claim 11 wherein the interconnect structure comprises a conductive link that conforms to at least a surface of the first package.

17. The assembly of claim 11 wherein the first and second bond-sites include outer edges laterally offset from one another.

18. The assembly of claim 1 wherein the inner edge of the first bond-site extends away from the axis by the first width and the inner edge of the second bond-site extends away from the axis by the second width.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
Priority Claims (1)
SG 200705093-3 · Jul 9, 2007 · national
Continuity (4)
Division 13441533 · Apr 6, 2012
Division 12973607 · Dec 20, 2010
Division 11846928 · Aug 29, 2007
Related Publication 20140124960A1 · May 8, 2014