Systems and methods for resolving clock time between asynchronous time domains

1. A method for resolving clock time between at least two asynchronous clock domains, the method comprising:

determining, via a digital circuit, at least a high resolution time period and a low resolution time period for a clock of a first time domain;

generating, via the digital circuit, a plurality of sequenced transition signals for the high resolution time period, wherein each sequenced transition signal corresponds to a respective bit transition period of the high resolution time period of the first time domain;

encoding, via the digital circuit, the plurality of sequenced transition signals for the high resolution time period into a high resolution vector; and

encoding, via the digital circuit, the low resolution time period into a low resolution vector.

2. The method of claim 1 , wherein the digital circuit is a first digital circuit, the method further comprising:

sampling the high resolution vector and the low resolution vector by a second digital circuit operating according to an asynchronous clock of a second time domain; and

decoding, via the second digital circuit, the high resolution vector and the low resolution vector to yield a tabulated clock time for the first time domain.

3. The method of claim 2 , wherein, sampling the high resolution vector further comprises:

sampling, via the second digital circuit, the encoded high resolution vector as a digital bus.

4. The method of claim 1 , wherein the digital circuit is a first digital circuit, the method further comprising:

continuously updating, via the first digital circuit, the high resolution vector and the low resolution vector to reflect a current clock time of the first time domain.

5. The method of claim 2 , wherein the high resolution time period of the clock of the first time domain is faster than the asynchronous clock of a second time domain.

6. The method of claim 2 , wherein the high resolution time period of the clock of the first time domain is comparable to the asynchronous clock of a second time domain.

7. The method of claim 2 , wherein each of the first digital circuit and the second digital circuit is selected from the group consisting of: a field programmable gate array device, an application-specific integrated circuit (ASIC) device, and a complex programmable logic devices (CPLD).

8. The method of claim 2 , wherein sampling the high resolution vector and the low resolution vector by a second digital circuit further comprises:

maintaining, via the first digital circuit, the low resolution vector as static when sampled.

9. A device operating according to a clock of a first time domain, the device comprising:

one or more network interfaces adapted to communicate in a communication network;

a processor adapted to execute one or more processes; and

a memory configured to store a process executable by the processor, the process when executed operable to:

determine at least a high resolution time period and a low resolution time period for a clock of a first time domain;

generate a plurality of sequenced transition signals for the high resolution time period, wherein each sequenced transition signal corresponds to a respective bit transition period of the high resolution time period of the first time domain;

encode the plurality of sequenced transition signals for the high resolution time period into a high resolution vector; and

encode the low resolution time period into a low resolution vector.

10. The device of claim 9 , wherein the process when executed is further operable to cause a second device, operating according to an asynchronous clock of a second time domain, to sample the high resolution vector and the low resolution vector, and decode the high resolution vector and the low resolution vector to yield a tabulated clock time for the first time domain.

11. The device of claim 10 , wherein the process when executed to cause the second device to sample the high resolution vector and the low resolution vector, further causes the second device to sample the encoded high resolution vector as a digital bus.

12. The device of claim 9 , wherein the process when executed is further operable to:

continuously update the high resolution vector and the low resolution vector to reflect a current clock time of the first time domain.

13. The device of claim 10 , wherein high resolution time period of the clock of the first time domain is faster than the asynchronous clock of the second time domain.

14. The device of claim 10 , wherein the device and the second device are selected from the group consisting of: a field programmable gate array device, an application-specific integrated circuit (ASIC) device, and a complex programmable logic devices (CPLD).

15. The device of claim 10 , wherein the process when executed to cause the second device to sample the high resolution vector and the low resolution vector, is further operable to:

maintain the low resolution vector as static when sampled by the second device.

16. A tangible, non-transitory, computer-readable media having software encoded thereon, the software, when executed by a processor, operable to:

determine at least a high resolution time period and a low resolution time period for a clock of a first time domain;

generate a plurality of sequenced transition signals for the high resolution time period, wherein each sequenced transition signal corresponds to a respective bit transition period of the high resolution time period of the first time domain;

encode the plurality of sequenced transition signals for the high resolution time period into a high resolution vector; and

encode the low resolution time period into a low resolution vector.

17. The tangible, non-transitory, computer-readable media of claim 16 , wherein the software, when executed by the processor is further operable to:

continuously update the high resolution vector and the low resolution vector to reflect a current clock time of the first time domain.