IP Library Granted Patent US 9,258,152
Granted Patent B2
US 9,258,152 · App. 14/154,789 · Granted Feb 9, 2016

Systems, circuits and methods for adapting parameters of a linear equalizer in a receiver

Inventors: Andrew Lin (Menlo Park, CA); Faramarz Bahmani (Palo Alto, CA)
Assignee: Broadcom Corporation
H04L25/03057
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Quick Facts
Patent No.
US 9,258,152
App. No.
14/154,789
Granted
Feb 9, 2016
Kind
B2
Abstract

A receiver is optimized by adapting parameters of a linear equalizer component within the receiver. Data decisions and error decisions are generated. These data decision and error decisions are used to derive an error rate of data by measuring the number of margin hits that occur. A balance value is also calculated from the data decisions and the error decisions. The balance value is used to update parameters of the linear equalizer. The updating of the parameter continues until the number of margin hits has been minimized.

Claims (35)

1. A receiver comprising:

a differential digital to analog converter that provides a coefficient to a decision feedback equalizer; and

a logic module configured to iteratively adapt the coefficient of the decision feedback equalizer based on decisions generated by the decision feedback equalizer until a bit-error rate is minimized.

2. The receiver of claim 1 , wherein the decision feedback equalizer comprises:

a data slicer configured to generate data decisions; and

an error slicer configured to generate error decisions,

wherein the decisions generated by the decision feedback equalizer comprise the data decisions and the error decisions.

3. The receiver of claim 1 , wherein the logic module is further configured to calculate the bit-error rate based on the decisions generated by the decision feedback equalizer.

4. The receiver of claim 1 , wherein the coefficient spans half of a maximum swing of an input to the decision feedback equalizer.

5. The receiver of claim 4 , wherein the decision feedback equalizer further comprises another coefficient, which spans half the span of the coefficient.

6. The receiver of claim 1 , wherein the logic module is further configured to adapt the coefficient using a steepest descent algorithm.

7. The receiver of claim 1 , wherein the logic module is further configured to adapt the coefficient using a least means square algorithm.

8. The receiver of claim 7 , wherein the logic module is further configured to calculate a balance of the coefficient based on the decisions generated by the decision feedback equalizer.

9. The receiver of claim 1 , further comprising:

a de-multiplexor configured to format the decisions generated by the decision feedback equalizer.

10. The receiver of claim 1 , wherein the differential digital to analog converter is an n-bit, true-zero differential digital to analog converter.

11. An integrated circuit comprising:

a transmitter configured to transmit data over a network; and

a receiver configured to receive data from the network, the receiver comprising:

a differential digital to analog converter that provides a coefficient to a decision feedback equalizer; and

a logic module configured to iteratively adapt the coefficient of the decision feedback equalizer based on decisions generated by the decision feedback equalizer until a bit-error rate is minimized.

12. The integrated circuit of claim 11 , wherein the integrated circuit is disposed in a network communication device.

13. A method for adapting a coefficient of a decision feedback equalizer, the method comprising:

receiving a plurality of decisions generated by a decision feedback equalizer;

adapting a coefficient, provided by a differential digital to analog converter, of the decision feedback equalizer based on the plurality of decisions; and

repeating the receiving and the adapting until a bit-error rate is minimized.

14. The method of claim 13 , wherein the plurality of decisions comprise a data decision and an error decision.

15. The method of claim 13 , further comprising calculating the bit-error rate based on the plurality of decisions.

16. The method of claim 15 , wherein the calculating the bit-error rate based on the plurality of decisions comprises:

determining margin hits based on the plurality of decisions, and

calculating the bit-error rate based on the margin hits.

17. The method of claim 13 , wherein the adapting the coefficient comprises using a steepest descent algorithm.

18. The method of claim 13 , wherein the adapting the coefficient comprises using a least means square algorithm.

19. The method of claim 18 , further comprising calculating a balance of the coefficient based on the plurality of decisions.

20. The method of claim 13 , further comprising formatting, by a de-multiplexor, the plurality of decisions generated by the decision feedback equalizer.

Assignments (9)
CORRECTIVE ASSIGNMENT TO CORRECT THE PATENT NUMBER 9,385,856 TO 9,385,756 PREVIOUSLY RECORDED AT REEL: 47349 FRAME: 001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 22, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 051144/0648 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE PREVIOUSLY RECORDED ON REEL 047229 FRAME 0408. ASSIGNOR(S) HEREBY CONFIRMS THE THE EFFECTIVE DATE IS 09/05/2018. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047349/0001 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047229/0408 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
CHANGE OF NAME Recorded Apr 8, 2015
From: NETLOGIC MICROSYSTEMS, INC.
To: NETLOGIC I LLC
Reel/Frame 035387/0234 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 8, 2015
From: NETLOGIC I LLC
To: BROADCOM CORPORATION
Reel/Frame 035358/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 21, 2014
From: LIN, ANDREW; BAHMANI, FARAMARZ
To: BROADCOM CORPORATION
Reel/Frame 034226/0415 →
Continuity (2)
Continuation 12973735 · Dec 20, 2010
Related Publication 20140126625A1 · May 8, 2014