Display device with de-multiplexers having different de-multiplex ratios

1. A display device, comprising:

a display area;

a plurality of data buses located in the display area;

a controller for providing a first data signal and a second data signal;

a first de-multiplexer having a first de-multiplex ratio, for outputting the first data signal received from the controller to a plurality of first data buses of the data buses; and

a second de-multiplexer having a second de-multiplex ratio, for outputting the second data signal received from the controller to a plurality of second data buses of the data buses;

wherein the first de-multiplex ratio is different from the second de-multiplex ratio.

2. The display device according to claim 1 , wherein the first and second de-multiplexers are applied in the display device according to the data bus loads of the data buses.

3. The display device according to claim 2 , wherein the first de-multiplex ratio is larger than the second de-multiplex ratio, and the data bus loads of the first data buses connected to the first de-multiplexer are less than the second data bus loads of the data buses connected to the second de-multiplexer.

4. The display device according to claim 3 , wherein the lengths of the first data buses are shorter than the lengths of the second data buses.

5. The display device according to claim 2 , wherein the first and second de-multiplexers comprise M and N output terminals connected to the data buses, respectively, the controller provides i clock signals to the first de-multiplexer through i clock wirings to select one of the M output terminals of the first de-multiplexer to output the first data signal to the first data bus, and provides j clock signals to the second de-multiplexer through j clock wirings to select one of the N output terminals of the second de-multiplexer to output the second data signal to the second data bus, where M, N, i and j are integers larger than 1, and N is less than M.

6. The display device according to claim 5 , wherein the controller provides the i clock signals to the first de-multiplexer sequentially, the rising time of a k th clock signal of the i clock signals in time sequence is overlapped with the rising time of a (k-1) th clock signal of the i clock signals in time sequence, where k is an integer larger than 1.

7. The display device according to claim 5 , wherein the first de-multiplexer further comprises M switching elements that each have an output wiring, the output wirings of the M switching elements are respectively coupled to the M output terminals of the first de-multiplexer; the second de-multiplexer further comprises N switching elements that each having an output wiring, the output wirings of the N switching elements are respectively coupled to the N output terminals of the second de-multiplexer.

8. The display device according to claim 7 , wherein the pulse width of the i clock signals provided to the first de-multiplexer is shorter than the pulse width of the j clock signals provided to the second de-multiplexer.

9. The display device according to claim 5 , wherein the clock wirings are co-used by the first and second de-multiplexers, so that the i clock signals provided to the first de-multiplexer are the same as the j clock signals provided to the second de-multiplexer, where i is equal to j.

10. The display device according to claim 9 , wherein the first de-multiplexer further comprises M switching elements that each having an output wiring, the output wirings of the M switching elements are respectively coupled to the M output terminals of the first de-multiplexer; the second de-multiplexer further comprise M switching elements that each having an output wiring, each L of the output wirings of the M switching elements of the second de-multiplexer is combined into one of the N output terminals of the second de-multiplexer, where L is an integer less than M.

11. The display device according to claim 9 , wherein the first de-multiplexer further comprises M switching elements that each having an output wiring, the output wirings of the M switching elements are respectively coupled to the M output terminals of the first de-multiplexer; the second de-multiplexer further comprise N switching elements that each having an output wiring, the output wirings of the N switching elements are respectively coupled to the N output terminals of the second de-multiplexer.

12. The display device according to claim 11 , wherein the M switching elements of the first de-multiplexer are controlled by the i clock signals, and the N switching elements of the second de-multiplexer are controlled by N clock signals of the i clock signals, the N clock signals of the i clock signals are co-used in the first and second de-multiplexers.

13. The display device according to claim 12 , wherein the pulse width of the clock signals used only in the first de-multiplexer is shorter than the pulse width of the clock signals co-used in the first and second de-multiplexers.

14. The display device according to claim 1 , wherein the first de-multiplexer ratio is larger than the second de-multiplexer ratio, and the controller provides the first and second data signals to the first and second de-multiplexers through a first data wiring and a second data wiring, respectively;

wherein the first and second data wirings have a first resistance and a second resistance, respectively, and the first resistance is less than the second resistance.

15. The display device according to claim 1 , wherein the display area is formed in a shape consisting of circle, shell, semicircle, oval, triangle, rhombus, trapezoid, polygon, and any combinations thereof.

16. The display device according to claim 1 , wherein the display device further comprises a third de-multiplexer for outputting a third data signal received from the controller to a third data bus of the data buses, wherein the third de-multiplexer has a third de-multiplex ratio which is larger than the second de-multiplex ratio and smaller than the first de-multiplex ratio.

17. The display device according to claim 16 , wherein the display device further comprises a border area adjacent to the display area, the border area is divided into a side edge area for disposing the first de-multiplexer, a middle area for disposing the second de-multiplexer, and an intermediate area for disposing the third de-multiplexer, wherein the intermediate area is located between the middle and side edge area.

18. The display device according to claim 1 , wherein the display area further comprises a border area adjacent to the display area, the border area is divided into a side edge area for disposing the first de-multiplexer, a middle area for disposing the second de-multiplexer, and an intermediate area for disposing a de-multiplexer combination of the first and second de-multiplexers, wherein the intermediate area is located between the middle and side edge area.

19. The display device according to claim 18 , wherein the de-multiplexer combination comprises:

a first de-multiplexer combination having a first combination ratio; and

a second de-multiplexer combination having a second combination ratio,

wherein the first de-multiplexer combination is disposed between the second de-multiplexer combination and the first de-multiplexer.

wherein the combination ratio is the quantity of the first de-multiplexer to the quantity of the second de-multiplexer, and the first combination ratio is larger than the second combination ratio.

20. The display device according to claim 19 , wherein the combination ratio in the intermediate area is increasing from an area adjacent to the middle area to another area adjacent to the side edge area.