IP Library Granted Patent US 9,281,266
Granted Patent B2
US 9,281,266 · App. 14/156,967 · Granted Mar 8, 2016

Stacked chip-on-board module with edge connector

Inventors: Wael Zohni (San Jose, CA); Belgacem Haba (Saratoga, CA)
Assignee: Tessera, Inc.
H01L23/49575G11C5/04G11C5/06H01L23/4951H01L24/73H01L25/0652H01L25/0657H01L25/105H01L25/50H01L23/13H01L24/13H01L24/16H01L24/29H01L24/32H01L24/48H01L2224/0401H01L2224/06135H01L2224/06136H01L2224/06156H01L2224/131H01L2224/16225H01L2224/16227H01L2224/2919H01L2224/32145H01L2224/32225H01L2224/32245H01L2224/4824H01L2224/4826H01L2224/48227H01L2224/73203H01L2224/73215H01L2224/73253H01L2224/73265H01L2225/0651H01L2225/06517H01L2225/06562H01L2225/06565H01L2225/1023H01L2924/01029H01L2924/01087H01L2924/01322H01L2924/07811H01L2924/1434H01L2924/181H01L2924/3011
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Quick Facts
Patent No.
US 9,281,266
App. No.
14/156,967
Granted
Mar 8, 2016
Kind
B2
Abstract

A module can include a module card and first and second microelectronic elements having front surfaces facing a first surface of the module card. The module card can also have a second surface and a plurality of parallel exposed edge contacts adjacent an edge of at least one of the first and second surfaces for mating with corresponding contacts of a socket when the module is inserted in the socket. Each microelectronic element can be electrically connected to the module card. The front surface of the second microelectronic element can partially overlie a rear surface of the first microelectronic element and can be attached thereto.

Claims (19)

1. A module, comprising:

a lead assembly having first and second opposed surfaces, each extending in a first direction and a second direction transverse to the first direction, and a plurality of exposed module contacts adjacent an edge of at least one of the first and second surfaces configured to mate with corresponding contacts of a socket, the lead assembly including first and second gaps extending between the first and second surfaces;

first and second microelectronic elements having front surfaces facing the first surface of the lead assembly, each microelectronic element having chip contacts electrically connected to the lead assembly, the front surface of the second microelectronic element partially overlying a rear surface of the first microelectronic element and attached thereto, the first microelectronic element having a lateral edge extending between the front and rear surfaces thereof and extending in the second direction, the front surface of the second microelectronic element projecting in the first direction beyond the lateral edge,

the second microelectronic element having first and second opposed edges extending between the front and rear surfaces of the second microelectronic element and extending in the second direction, the front surface of the second microelectronic element having a first outer region adjacent the first edge, a second outer region adjacent the second edge, and a central region disposed between the first and second outer regions, each of the first and second outer regions and the central region having equal width such that the central region extends a middle third of a distance between the first and second edges, the chip contacts of the second microelectronic element disposed in the central region beyond the lateral edge of the first microelectronic element;

first wire bonds extending through the first gap and coupled to the chip contacts of the first microelectronic element, and second wire bonds extending through the second gap and coupled to the chip contacts of the second microelectronic element, the edge contacts being coupled to the first and second microelectronic elements through the first and second wire bonds; and

an encapsulant covering the first and second microelectronic elements and a portion of the lead assembly.

2. The module as claimed in claim 1 , wherein chip contacts of the second microelectronic element are exposed within a central region of the front surface of the second microelectronic element.

3. The module as claimed in claim 2 , wherein chip contacts of the first microelectronic element are exposed within a central region of the front surface of the first microelectronic element.

4. The module as claimed in claim 1 , wherein the first microelectronic element has a second edge opposed to the lateral edge, the front surface of the first microelectronic element and the lateral and second edges of the first microelectronic element being such that:

the front surface of the first microelectronic element has a first outer region adjacent the lateral edge of the first microelectronic element, a second outer region adjacent the second edge of the first microelectronic element, and a central region disposed between the first and second outer regions of the front surface of the first microelectronic element, each of the first and second outer regions and the central region having equal width such that the central region of the first microelectronic element extends a middle third of a distance between the lateral and second edges, wherein the chip contacts of the first microelectronic element are disposed in such central region.

5. The module as claimed in claim 1 , wherein at least one of the first and second microelectronic elements includes a memory storage element.

6. The module as claimed in claim 5 , wherein the lead assembly includes portions of leads extending from address input chip contacts of the at least one of the first and second microelectronic elements to a subset of the edge contacts, wherein the subset of the edge contacts are configured to carry an address signal usable to address the memory storage element in at least one of the first and second microelectronic elements.

7. The module as claimed in claim 1 , wherein at least some of the edge contacts are configured to carry at least one of a signal or a reference potential between the respective edge contact and signal or reference potential chip contacts of each of the first and second microelectronic elements.

8. The module as claimed in claim 1 , wherein at least one of the first and second microelectronic elements is flip chip bonded to the lead assembly.

9. The module as claimed in claim 1 , further comprising a plurality of third microelectronic elements, each third microelectronic element being electrically connected to the lead assembly.

10. The module as claimed in claim 9 , wherein the plurality of third microelectronic elements are arranged in a stacked configuration, each of the third microelectronic elements having a front or rear surface confronting a front or rear surface of an adjacent one of the third microelectronic elements.

11. The module as claimed in claim 9 , wherein the plurality of third microelectronic elements are arranged in a planar configuration, each of the third microelectronic elements having a peripheral surface confronting a peripheral surface of an adjacent one of the third microelectronic elements.

12. The module as claimed in claim 9 , wherein the second microelectronic element includes volatile RAM, the third microelectronic elements each include nonvolatile flash memory, and the first microelectronic element includes a processor having structure therein that is configured to predominantly control transfers of data between an external component and the second and third microelectronic elements.

13. The module as claimed in claim 9 , wherein the second microelectronic element includes a volatile frame buffer memory storage element, the third microelectronic elements each include nonvolatile flash memory, and the first microelectronic element includes a graphics processor.

Assignments (6)
CHANGE OF NAME Recorded Nov 21, 2025
From: TESSERA, INC.
To: TESSERA LLC
Reel/Frame 073658/0373 →
CHANGE OF NAME Recorded Nov 21, 2025
From: TESSERA LLC
To: ADEIA SEMICONDUCTOR SOLUTIONS LLC
Reel/Frame 073658/0816 →
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION; TESSERA ADVANCED TECHNOLOGIES, INC; DTS, INC.; DTS LLC; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
Reel/Frame 052920/0001 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
SECURITY INTEREST Recorded Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.; DIGITALOPTICS CORPORATION; DIGITALOPTICS CORPORATION MEMS; DTS, LLC; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 28, 2014
From: ZOHNI, WAEL; HABA, BELGACEM
To: TESSERA, INC.
Reel/Frame 032321/0940 →
Continuity (3)
Division 13306203 · Nov 29, 2011
Provisional Application 61477820 · Apr 21, 2011
Related Publication 20140131849A1 · May 15, 2014