Non-systematic coded error correction
View Patent ↗Methods are described that facilitate the detection and correction of data in memory systems or devices by encoding the data bits of a memory row or block in a non-systematic ECC code. This allows memory embodiments of the present invention to utilize reduced complexity error detection and correction hardware and/or routines to efficiently detect and correct corrupted user data in a segment of memory, such as a sector, word line row, or erase block. User data is not stored in a plaintext format in the memory array, allowing for an increased level of data security. The ECC code is distributed throughout the stored data in the memory segment, increasing the robustness of the ECC code and its resistance to damage or data corruption.
1. A method of encoding a data segment with a transform matrix for storage to a memory, the method comprising:
inputting a data segment into a non-systematic error correction code (ECC) transform matrix to output a non-systematic ECC encoded data segment, wherein the transform matrix distributes the ECC encoding across the non-systematic ECC encoded data segment; and
storing the non-systematic ECC encoded data segment to the memory.
2. The method of claim 1 , wherein inputting a data segment into a non-systematic ECC transform matrix to output a non-systematic ECC encoded data segment further comprises inputting a data segment into a non-systematic ECC transform matrix to output a non-systematic ECC encoded data segment, where the transform matrix does not contain a unity core square matrix.
3. The method of claim 1 , wherein inputting a data segment into a non-systematic ECC transform matrix to output a non-systematic ECC encoded data segment further comprises inputting a data segment into a non-systematic ECC transform matrix to output a non-systematic ECC encoded data segment, where the transform matrix localizes the ECC codes generated in the encoding in two or more areas in the non-systematic ECC encoded data segment.
4. The method of claim 1 , wherein the non-systematic ECC code encoded with is one of a non-systematic Hamming code, a non-systematic Reed-Solomon (R-S) code, a non-systematic Bose-Chaudhuri-Hocquenghem (BCH) code, a non-systematic circular redundancy code (CRC-32), a non-systematic Golay code, a non-systematic Reed-Muller code, a non-systematic Goppa code, and a non-systematic Denniston code.
5. A memory system, comprising:
at least one memory device, wherein the at least one memory device contains a memory array with a plurality of memory cells arranged in one or more data segments;
a memory control circuit coupled to the at least one memory device, wherein the memory control circuit is configured to input a data segment into a non-systematic error correction code (ECC) transform matrix and to encode the data segment with the non-systematic ECC transform matrix to generate a non-systematic ECC encoded data segment, wherein the non-systematic ECC transform matrix distributes the ECC encoding across the non-systematic ECC encoded data segment, and to store the non-systematic ECC encoded data segment to a memory device of the at least one memory device.
6. The memory system of claim 5 , wherein the memory control circuit is configured to encode the data segment by inputting the data segment into the non-systematic ECC transform matrix to output the non-systematic ECC encoded data segment.
7. The memory system of claim 6 , wherein the non-systematic ECC transform matrix does not contain a unity core square matrix.
8. The memory system of claim 6 , wherein the non-systematic ECC transform matrix localizes the ECC codes generated in the encoding in two or more areas in the non-systematic ECC encoded data segment.
9. The memory system of claim 5 , wherein the memory control circuit is further configured to encode the data segment with one of a non-systematic Hamming code, a non-systematic Reed-Solomon (R-S) code, a non-systematic Bose-Chaudhuri-Hocquenghem (BCH) code, a non-systematic circular redundancy code (CRC-32), a non-systematic Golay code, a non-systematic Reed-Muller code, a non-systematic Goppa code, and a non-systematic Denniston code.
10. A memory device comprising:
a memory array containing a plurality of memory cells arranged into a plurality of segments;
a data buffer;
a host transfer circuit coupled to the data buffer; and
an error correction code (ECC) generator/checker circuit, wherein the memory device is adapted to input a data segment into a non-systematic ECC transform matrix and to encode the data segment with the non-systematic ECC transform matrix and store the non-systematic ECC encoded data segment to the memory array, wherein the non-systematic ECC transform matrix distributes the ECC encoding across the non-systematic ECC encoded data segment, and wherein the ECC generator/checker circuit is adapted to receive and decode the non-systematic ECC encoded data segment from the memory array and output to the data buffer.
11. The memory device of claim 10 , wherein the memory device is configured to encode the data segment by inputting the data segment into the non-systematic ECC transform matrix to output a non-systematic ECC encoded data segment.
12. The memory device of claim 11 , wherein the non-systematic ECC transform matrix does not contain a unity core square matrix.
13. The memory device of claim 11 , wherein the non-systematic ECC transform matrix localizes the ECC codes generated in the encoding in two or more areas in the non-systematic ECC encoded data segment.
14. The memory device of claim 10 , wherein the memory device is further configured to encode the data segment with one of a non-systematic Hamming code, a non-systematic Reed-Solomon (R-S) code, a non-systematic Bose-Chaudhuri-Hocquenghem (BCH) code, a non-systematic circular redundancy code (CRC-32), a non-systematic Golay code, a non-systematic Reed-Muller code, a non-systematic Goppa code, and a non-systematic Denniston code.