Dummy gate structure for electrical isolation of a fin DRAM
Trench capacitors can be formed between lengthwise sidewalls of semiconductor fins, and source and drain regions of access transistors are formed in the semiconductor fins. A dummy gate structure is formed between end walls of a neighboring pair of semiconductor fins, and limits the lateral extent of raised source and drain regions that are formed by selective epitaxy. The dummy gate structure prevents electrical shorts between neighboring semiconductor fins. Gate spacers can be formed around gate structures and the dummy gate structures. The dummy gate structures can be replaced with dummy replacement gate structures or dielectric material portions, or can remain the same without substitution of any material. The dummy gate structures may consist of at least one dielectric material, or may include electrically floating conductive material portions.
1. A semiconductor structure comprising:
semiconductor fins located on a substrate, wherein each of said semiconductor fins is laterally bound by a pair of lengthwise sidewalls and a pair of widthwise sidewalls;
trench capacitors located within said substrate, wherein an inner electrode of each trench capacitor is electrically shorted to a source region in one of said semiconductor fins;
a gate structure straddling one of said semiconductor fins and overlying one of said trench capacitors, said gate structure comprising a stack of a gate dielectric and a gate electrode;
a gate spacer laterally surrounding said gate dielectric and said gate electrode; and
a dummy gate structure including dielectric surfaces located between a widthwise sidewall of one of said semiconductor fins and a widthwise sidewall of another of said semiconductor fins, and between a sidewall of one of said trench capacitors and a sidewall of another of said trench capacitors, said dummy gate structure laterally extending along a same direction as said gate structure.
2. The semiconductor structure of claim 1 , further comprising a dummy gate spacer laterally surrounding said dummy gate structure, wherein said dummy gate spacer is in contact with said widthwise sidewall of said semiconductor fins and said widthwise sidewall of said another of said semiconductor fins, and said dielectric surfaces are provided by said dummy gate spacer.
3. The semiconductor structure of claim 2 , wherein said dummy gate spacer has a same composition and a same lateral thickness as said gate spacer.
4. The semiconductor structure of claim 2 , wherein said dummy gate structure comprises:
a dielectric liner having a same thickness and a same composition as said gate dielectric; and
a conductive material portion having a same composition as said gate electrode and embedded within said dielectric liner.
5. The semiconductor structure of claim 2 , wherein said dummy gate structure comprises a dielectric material portion including a different material than said gate dielectric, wherein said dielectric material portion is in contact with said widthwise sidewall of said semiconductor fins and said widthwise sidewall of said another of said semiconductor fins, and said dielectric surfaces are provided by said dielectric material portion.
6. The semiconductor structure of claim 5 , wherein an entirety of said dummy gate structure consists of said dielectric material portion.
7. The semiconductor structure of claim 5 , wherein said dummy gate structure comprises:
a dielectric liner having a different composition than said gate dielectric; and
an insulator material portion contacting inner sidewalls of said dummy gate spacer.
8. The semiconductor structure of claim 2 , further comprising:
a source region located within said one of said semiconductor fins and contacting said dummy gate structure; and
a raised source region contacting sidewalls and a top surface of said source region and a sidewall of said gate spacer and a sidewall of said dummy gate spacer.
9. The semiconductor structure of claim 2 , further comprising a conductive strap structure electrically shorting a source region in said one of said semiconductor fins and an inner electrode in one of said trench capacitors and contacting said dummy gate spacer.
10. The semiconductor structure of claim 1 , further comprising a shallow trench isolation layer in contact with a bottom surface of said dummy gate structure.