Hierarchical global clock tree
Methods, systems, and circuits for forming and operating a global hierarchical clock tree are described. The global hierarchical clock tree may comprise a clock circuit that operates to provide clock signals to a core circuit surrounded by the clock circuit. The clock circuit may include two or more first and second clock generator modules to generate a first and a second set of clock signals, respectively. The first and second clock modules may be located so that the first set of clock signals experience approximately equal first latencies and the second set of clock signals experience approximately equal second latencies. Additional methods, systems, and circuits are disclosed.
1. An integrated circuit comprising:
a clock circuit configured to provide clock signals to a core circuit, the clock circuit comprising:
a plurality of clock-generator modules configured to generate a plurality of first-level clock signals; and
a hierarchy of clock modules arranged in one or more levels including a first level, each level including a plurality of clock modules that are each configured to receive at least one clock signal corresponding to that level and to generate at least one next-level clock signal, and the clock modules at each level being arranged to provide approximately equal latencies for the next-level clock signals at that level.
2. The integrated circuit of claim 1 , wherein the one or more levels include the first level and a second level, the first-level clock modules providing second-level clock signals as inputs to the second-level clock modules.
3. The integrated circuit of claim 1 , wherein the clock circuit substantially surrounds the core circuit, and the core circuit receives at least two clock signals from at least two levels in the hierarchy of clock modules.
4. The integrated circuit of claim 1 , wherein the core circuit includes an asynchronous circuit.
5. The integrated circuit of claim 1 , wherein each clock-generator module is located proximate to a corner of the core circuit.
6. The integrated circuit of claim 1 , wherein each first-level clock module receives first-level clock signals from two clock-generator modules that are located at approximately equal distances from that first-level clock module.
7. The integrated circuit of claim 1 , wherein
the one or more levels include the first level and a second level,
each first-level clock module receives first-level clock signals from two clock-generator modules that are located at approximately equal distances from that first-level clock module, and
each second-level clock module receives second-level clock signals from two first-level clock modules that are located at approximately equal distances from that second-level clock module.
8. The integrated circuit of claim 1 , wherein each clock-generator module includes a global clock generator.
9. The integrated circuit of claim 1 , wherein each clock-generator module includes a phase-locked loop (PLL) that has output nodes connected to a plurality of programmable clock dividers.
10. A method of providing clock signals to a core circuit, the method comprising:
generating, by a plurality of clock-generator modules, a plurality of first-level clock signals; and
receiving, by a modular clock hierarchy comprising one or more levels including a first level, clock signals corresponding to each level and generating a plurality of corresponding next-level clock signals, each level including a plurality of clock modules that are each configured to receive at least one clock signal corresponding to that level and to generate at least one next-level clock signal, and the clock modules at each level being arranged to provide approximately equal latencies for the next-level clock signals at that level.
11. The method of claim 10 , wherein the one or more levels include the first level and a second level, the first-level clock modules providing second-level clock signals as inputs to the second-level clock modules.
12. The method of claim 10 , wherein the clock circuit substantially surrounds the core circuit, and the core circuit receives at least two clock signals from at least two levels in the hierarchy of clock modules.
13. The method of claim 10 , wherein the core circuit includes an asynchronous circuit.
14. The method of claim 10 , wherein each clock-generator module is located proximate to a corner of the core circuit.
15. The method of claim 10 , wherein each first-level clock module receives first-level clock signals from two clock-generator modules that are located at approximately equal distances from that first-level clock module.
16. The method of claim 10 , wherein
the one or more levels include the first level and a second level,
each first-level clock module receives first-level clock signals from two clock-generator modules that are located at approximately equal distances from that first-level clock module, and
each second-level clock module receives second-level clock signals from two first-level clock modules that are located at approximately equal distances from that second-level clock module.
17. The method of claim 10 , wherein each clock-generator module includes a global clock generator.
18. The method of claim 10 , wherein each clock-generator module includes a phase-locked loop (PLL) that has output nodes connected to a plurality of programmable clock dividers.
19. A non-transitory machine-readable medium that stores instructions, that when executed by a machine cause the machine to perform operations for providing clock signals to a core circuit, the operations comprising:
generating, by a plurality of clock-generator modules, a plurality of first-level clock signals; and
receiving, by a modular clock hierarchy comprising one or more levels including a first level, clock signals corresponding to each level and generating a plurality of corresponding next-level clock signals, each level including a plurality of clock modules that are each configured to receive at least one clock signal corresponding to that level and to generate at least one next-level clock signal, and the clock modules at each level being arranged to provide approximately equal latencies for the next-level clock signals at that level.