Semiconductor memory devices, memory systems including the same and method of writing data in the same
In one embodiment, the semiconductor device includes a memory array and a control architecture configured to control reading data from and writing data to the memory array. The control architecture is configured to receive data and a codeword location in the memory array, select one or more data units in the received data based on a data mask, read a codeword currently stored at the codeword location in the memory array, error correct the read codeword to generate a corrected read codeword, form a new codeword from the selected data units of the received data and data units in the corrected read codeword that do not correspond to the selected data units, and write the new codeword to the memory array.
1. A semiconductor device, comprising:
a memory array; and
a control architecture configured to control reading data from and writing data to the memory array, the control architecture configured to,
receive data and a codeword location in the memory array;
select one or more data units in the received data based on a data mask;
read a codeword currently stored at the codeword location in the memory array;
error correct the read codeword to generate a corrected read codeword;
form a new codeword from the selected data units of the received data and data units in the corrected read codeword that do not correspond to the selected data units; and
write the new codeword to the memory array.
2. The semiconductor device of claim 1 , wherein the control architecture is configured to receive the data mask.
3. The semiconductor device of claim 2 , wherein the control architecture is configured to receive the data mask from an external device.
4. The semiconductor device of claim 2 , wherein the control architecture is configured to perform the selecting by selecting the data units in the received data not masked by the data mask.
5. The semiconductor device of claim 1 , wherein the control architecture is configured to generate the data mask.
6. The semiconductor device of claim 5 , wherein the control architecture is configured to generate the data mask when the received data has a size less than a size of a codeword.
7. The semiconductor device of claim 5 , wherein the control architecture is configured to generate the data mask based on a received address.
8. The semiconductor device of claim 5 , wherein the control architecture is configured to perform the selecting by selecting the data units in the received data not masked by the data mask.
9. The semiconductor device of claim 1 , wherein the control architecture is configured to receive an address for the codeword location, and the control architecture is configured to read the read codeword based on the received address.
10. The semiconductor device of claim 1 , wherein the control architecture is configured to perform the error correcting based on parity information in the read codeword.
11. The semiconductor device of claim 10 , wherein the control architecture is configured to perform the forming by generating new parity bits, and to include the new parity bits in the new codeword.
12. The semiconductor device of claim 1 , wherein the control architecture is configured to perform the forming by generating new parity bits, and to include the new parity bits in the new codeword.
13. The semiconductor device of claim 1 , wherein the read codeword includes a message information portion and a parity information portion.
14. The semiconductor device of claim 13 , wherein the message information portion includes a plurality of data units.
15. The semiconductor device of claim 14 , wherein each of the data units is a byte.
16. The semiconductor device of claim 1 , wherein
the memory array includes a plurality of chips; and
the read codeword is stored across more than one chip in the memory array.
17. A memory system, comprising:
a plurality of memory chips,
wherein each memory chip includes,
a memory array; and
a control architecture configured to control reading data from and writing data to the memory array, the control architecture configured to,
receive data and a codeword location in the memory array;
select one or more data units in the received data based on a data mask;
read a codeword currently stored at the codeword location in the memory array;
error correct the read codeword to generate a corrected read codeword;
form a new codeword from the selected data units of the received data and data units in the corrected read codeword that do not correspond to the selected data units; and
write the new codeword to the memory array.
18. A method of operating a semiconductor device, comprising:
receiving data and a codeword location in a memory array;
selecting one or more data units in the received data based on a data mask;
reading a codeword currently stored at the codeword location in the memory array;
error correcting the read codeword to generate a corrected read codeword;
forming a new codeword from the selected data units of the received data and data units in the corrected read codeword that do not correspond to the selected data units; and
writing the new codeword to the memory array.
19. The method of claim 18 , wherein further comprising:
receiving the data mask.
20. The method of claim 19 , wherein the receiving the data mask receives the data mask from an external device.
21. The method of claim 19 , wherein the selecting selects the data units in the received data not masked by the data mask.
22. The method of claim 18 , further comprising:
generating the data mask.
23. The method of claim 22 , wherein the generating generates the data mask when the received data has a size less than a size of a codeword.
24. The method of claim 22 , wherein the generating generates the data mask based on a received address.
25. The method of claim 22 , wherein the selecting selects the data units in the received data not masked by the data mask.
26. The method of claim 18 , wherein the receiving receives an address for the codeword location, and the reading reads the read codeword based on the received address.
27. The method of claim 18 , wherein the error correcting error corrects based on parity information in the read codeword.
28. The method of claim 27 , wherein the forming generates new parity bits, and includes the new parity bits in the new codeword.
29. The method of claim 18 , wherein the forming generates new parity bits, and includes the new parity bits in the new codeword.
30. The method of claim 18 , further comprising:
at least one of receiving and generating the data mask.
31. The method of claim 18 , wherein the read codeword includes a message information portion and a parity information portion.
32. The method of claim 31 , wherein the message information portion includes a plurality of data units.
33. The method of claim 32 , wherein each of the data units is a byte.
34. The method of claim 18 , wherein
the memory array includes a plurality of chips; and
the reading reads portions of the read codeword from more than one chip in the memory array.