Methods and apparatuses with vertical strings of memory cells and support circuitry
Apparatuses and methods have been disclosed. One such apparatus includes strings of memory cells formed on a topside of a substrate. Support circuitry is formed on the backside of the substrate and coupled to the strings of memory cells through vertical interconnects in the substrate. The vertical interconnects can be transistors, such as surround substrate transistors and/or surround gate transistors.
1. An apparatus comprising:
a plurality of strings of memory cells on a top side of a substrate; and
support circuitry on a back side of the substrate and coupled to the plurality of strings of memory cells through the substrate, wherein the support circuitry is coupled to the plurality of strings of memory cells through a surround substrate transistor (SST) formed in the substrate.
2. The apparatus of claim 1 wherein the support circuitry is complementary metal oxide semiconductor (CMOS) circuitry.
3. The apparatus of claim 1 wherein each of the plurality of strings of memory cells comprises a respective semiconductor pillar extending outward from the substrate.
4. The apparatus of claim 1 wherein the support circuitry is memory support circuitry.
5. The apparatus of claim 1 wherein the plurality of strings of memory cells comprise a plurality of strings of memory cells extending outward from the substrate wherein a source of the plurality of strings of memory cells is above the plurality of strings of memory cells and a data line coupled to the plurality of strings of memory cells is between the substrate and the plurality of strings of memory cells.
6. The apparatus of claim 1 and further comprising a diffusion region on the topside of the substrate, the diffusion region having an opposite conductivity from the substrate, wherein the plurality of strings of memory cells comprise a plurality of strings of memory cells coupled to the diffusion region.
7. The apparatus of claim 6 wherein the diffusion region is a source for the plurality of strings of memory cells.
8. The apparatus of claim 1 , wherein the SST comprises a transfer gate of a charge pump circuit.
9. The apparatus of claim 1 , wherein the SST comprises a data line clamp transistor.
10. The apparatus of claim 1 , wherein the SST is used as a capacitor of a charge pump circuit.
11. The apparatus of claim 1 , wherein the support circuitry comprises at least one of page buffers and decoders.
12. The apparatus of claim 1 , wherein a channel length of the SST is shorter than a thickness of the substrate.
13. The apparatus of claim 1 , wherein the SST has a circular source/drain region on the topside of the substrate and a circular source/drain region on the backside of the substrate.
14. The apparatus of claim 1 , wherein the SST comprises a center SST and further comprising a plurality of outer SSTs in a circular pattern around the center SST.
15. The apparatus of claim 1 wherein the support circuitry is further coupled to the plurality of strings of memory cells through a data line and a conductor coupled to the SST.
16. The apparatus of claim 1 , wherein the support circuitry is further coupled to the plurality of strings of memory cells through an access line and a conductor coupled to the SST.
17. The apparatus of claim 1 , wherein the support circuitry is further coupled to the plurality of strings of memory cells through a select gate and a conductor coupled to the SST.
18. An apparatus comprising:
a substrate comprising:
a plurality of vertical interconnects connecting a topside of the substrate with a backside of the substrate; and
a plurality of wells in the substrate;
a plurality of strings of memory cells extending from the topside; and
support circuitry associated with the plurality of wells on the backside and coupled to the plurality of strings of memory cells through the vertical interconnects, wherein diffusion regions for the support circuitry are implanted into the plurality of wells on the backside.
19. The apparatus of claim 18 wherein the plurality of strings of memory cells are coupled to data lines that are on both the topside and the backside of the substrate.
20. The apparatus of claim 19 wherein the plurality of data lines comprise global data lines and local data lines and the global data lines are on the backside and the local data lines are on the topside.
21. The apparatus of claim 18 wherein the vertical interconnects comprise surround substrate transistors that couple the support circuitry to the plurality of strings of memory cells.
22. An apparatus comprising:
a plurality of strings of memory cells on a top side of a substrate; and
support circuitry on a back side of the substrate and coupled to the plurality of strings of memory cells through the substrate, wherein the support circuitry is coupled to the plurality of strings of memory cells through a surround gate transistor (SGT) formed in the substrate.