Insulated semiconductor faceplate designs

1. A semiconductor processing chamber faceplate comprising:

a conductive plate defining a plurality of apertures; and

a plurality of inserts, wherein each aperture of the plurality of apertures contains an insert of the plurality of inserts, wherein each insert of the plurality of inserts defines at least two channels there through, wherein each channel of the at least two channels independently extends vertically from a first end of an associated insert to a second end of the associated insert, wherein each channel of the at least two channels is radially offset from a central axis through the insert defining the at least two channels, and wherein the at least two channels are radially offset from one another about the central axis;

a plurality of first o-rings positioned within annular channels at least partially defined by the conductive plate within the plurality of aperture;

wherein a portion of each first o-ring of the plurality of first o-rings is seated within a first annular groove defined along a region of a corresponding insert between a top and bottom of the corresponding insert.

2. The faceplate of claim 1 , wherein the at least two channels defines six channels through the corresponding insert arranged in a hexagonal pattern.

3. The faceplate of claim 1 , wherein a second o-ring is seated within a second annular groove defined along the region of the corresponding insert between the top and bottom of the corresponding insert.

4. The faceplate of claim 1 , wherein the plurality of first o-rings are disposed within the plurality of inserts, wherein the plurality of inserts are housed within respectively defined apertures of the plurality of apertures of the conductive plate and extend radially within each aperture to within at least 50 mils of a radius of each aperture.

5. The faceplate of claim 1 , wherein at least a portion of each aperture of the plurality of apertures is defined with a decreasing diameter from an upper region to a lower region to define a tapered region.

6. The faceplate of claim 1 , further comprising a layer of dielectric material on all surfaces of the conductive plate configured to be exposed to a plasma.

7. The faceplate of claim 6 , wherein the layer of dielectric material is located on all surfaces of the conductive plate including on all surfaces defining the plurality of apertures.

8. The faceplate of claim 1 , wherein the plurality of first o-rings are each positioned radially outward from each insert of the plurality of inserts.

9. The faceplate of claim 1 , wherein each channel of the annular channels is partially defined by the conductive plate within an individual aperture of the plurality of apertures defined within the conductive plate, and wherein each channel of the annular channels is partially defined by the insert contained within each individual aperture.

10. A semiconductor processing chamber faceplate comprising:

a conductive plate defining a plurality of apertures; and

a plurality of inserts, wherein each insert of the plurality of inserts is disposed within a separate aperture of the plurality of apertures, wherein each aperture of the plurality of apertures is defined with an upper portion and a lower portion within the conductive plate, wherein a ledge is defined by the conductive plate at a boundary between the upper portion and the lower portion, wherein the upper portion is characterized by a cylindrical shape having a first diameter extending from a first end of the aperture to the ledge, and the lower portion is characterized by a cylindrical shape having a second diameter extending from the ledge to a second end of the aperture, wherein the second diameter is less than the first diameter, wherein each insert of the plurality of inserts defines a channel there through, and wherein the channel is characterized by a diameter less than or equal to the second diameter;

wherein each insert is seated on the defined ledge of each corresponding aperture, and wherein each insert occupies at least a portion of both the upper portion and lower portion of each aperture;

wherein a plurality of o-rings are positioned to form a seal between the plurality of inserts and a portion of the plate defining the upper portion of the aperture.

11. The faceplate of claim 10 , wherein each insert of the plurality of inserts comprises a dielectric material.

12. The faceplate of claim 11 , wherein the dielectric material comprises a ceramic including one or more of aluminum oxide (AI 2 O 3 ), zirconium oxide (ZrO 2 ), and yttrium oxide (Y 2 O 3 ).

13. The faceplate of claim 10 , wherein the ledge defines a transition from the first diameter to the second diameter.