Data-driven noise reduction technique for analog to digital converters
A successive operation register (SAR) analog-to-digital converter (ADC) circuit includes a bit reliability circuit that detects a delay time of the voltage comparator and, if the detected delay time is greater than a delay threshold time τ MV , outputs a bit reliability decision signal; a digital noise reduction circuit that is selectively activated if the bit reliability decision signal indicates the detected delay time is greater than the delay threshold time τ MV and produces a noise-reduced decision output that supersedes the decision output of the voltage comparator. In a preferred embodiment, the digital noise reduction circuit uses a multiple voting logic to produce a majority vote value as the noise-reduced decision output.
1. A successive operation register (SAR) analog-to-digital converter (ADC) circuit comprising:
a voltage comparator having a first analog signal input, a second analog input, and a decision output;
a decision logic circuit having an input connected to the decision output of the voltage comparator and a digital output;
a digital-to-analog converter (DAC) having a digital input connected to the digital output of the decision logic circuit and an analog output connected to the second analog input of the voltage comparator;
further comprising:
a bit reliability circuit that detects a delay time of the voltage comparator and, if the detected delay time is greater than a delay threshold time τ MV , outputs a bit reliability decision signal;
a digital noise reduction circuit that is selectively activated if the bit reliability decision signal indicates the detected delay time is greater than the delay threshold time τ MV and produces a noise-reduced decision output that supersedes the decision output of the voltage comparator.
2. The ADC circuit of claim 1 wherein the the digital-to-analog converter (DAC) has a second analog output connected to the first analog input of the voltage comparator.
3. The ADC circuit of claim 1 wherein the digital noise reduction circuit uses a multiple voting logic to produce a majority vote value as the noise-reduced decision output.
4. The ADC circuit of claim 3 wherein the digital noise reduction circuit is configurable in a number of repeated votes (Nv) per bit decision used in the voting logic and a number of voting cycles (Nc) per conversion used in the voting logic.
5. The ADC circuit of claim 4 further comprising a feedback circuit that controls τ MV of the bit reliability circuit based in part on the number of voting cycles (Nc) per conversion.
6. The ADC circuit of claim 3 further comprising an oscillation circuit that generates a variable over-sampled clock signal for the multiple voting logic.