Gate stack having electron blocking layers on charge storage layers for electronic devices
View Patent ↗Methods and apparatuses for electronic devices such as non-volatile memory devices are described. The memory devices include a multi-layer control dielectric, such as a double or triple layer. The multi-layer control dielectric includes a combination of high-k dielectric materials such as aluminum oxide, hafnium oxide, and/or hybrid films of hafnium aluminum oxide. The multi-layer control dielectric provides enhanced characteristics, including increased charge retention, enhanced memory program/erase window, improved reliability and stability, with feasibility for single or multi state (e.g., two, three or four bit) operation.
1. A gate stack comprising the following layers in successive order:
a first dielectric layer comprising a tunneling dielectric layer;
a charge storage layer on the first dielectric layer;
a second dielectric layer comprising a high-k dielectric material on the charge storage layer;
a third dielectric layer comprising SiO 2 on the second dielectric layer;
a fourth dielectric layer comprising Si 3 N 4 on the third dielectric layer;
a fifth dielectric layer comprising SiO 2 on the fourth dielectric layer, and
a sixth dielectric layer comprising a high-k dielectric material on the fifth dielectric layer,
wherein each of the second and the sixth dielectric layers comprises a metal oxide or a metal silicate.
2. The gate stack of claim 1 , wherein the charge storage layer comprises nanocrystals having a size less than 5 nm.
3. The gate stack of claim 1 , wherein the charge storage layer comprises a continuous floating gate.
4. The gate stack of claim 1 , wherein each of the third, fourth, and fifth dielectric layers has a thickness of 3 nm or less.
5. The gate stack of claim 1 , wherein each of the second and the sixth dielectric layers has a thickness of 2 nm or less.
6. The gate stack of claim 1 , wherein each of the second and the sixth dielectric layers comprises one of hafnium and zirconium.
7. The gate stack of claim 1 , wherein at least one of the second and the sixth dielectric layers comprises a metal silicate.
8. The gate stack of claim 7 , wherein the metal silicate is selected from the group consisting of a hafnium silicate and an aluminum silicate.
9. The gate stack of claim 1 , further comprising a seventh dielectric layer of 1 nm or less in thickness disposed between at least one of: (a) the second dielectric layer and the third dielectric layer; and (b) the fifth dielectric layer and the sixth dielectric layer.
10. The gate stack of claim 9 , wherein the seventh dielectric layer comprises aluminum oxide.
11. The gate stack of claim 2 , wherein the nanocrystals comprise ruthenium nanocrystals.