In System Reflow of Low Temperature Eutectic Bond Balls
Low temperature bond balls connect two structures having disparate coefficients of linear thermal expansion. An integrated circuit is made to heat the device such that the low temperature bond balls melt. After melting, the bond balls solidify, and the device is operated with the bond balls solidified. In one example, one of the two structures is a semiconductor substrate, and the other structure is a printed circuit board. The integrated circuit is a die mounted to the semiconductor substrate. The bond balls include at least five percent indium, and the integrated circuit is an FPGA loaded with a bit stream. The bit stream configures the FPGA such that the FPGA has increased power dissipation, which melts the balls. After the melting, a second bit stream is loaded into the FPGA and the FPGA is operated in a normal user-mode using the second bit stream.
1 - 17 . (canceled)
18 . A method comprising:
(a) supplying a first bit-stream for a Field Programmable Gate Array (FPGA), wherein the first bit-stream is adapted to configure the FPGA to increase a power dissipation of a plurality of logic gates of the FPGA such that a temperature of a device is increased thereby melting a plurality of bond balls, wherein the device comprises the FPGA and the plurality of bond balls.
19 . The method of claim 18 , further comprising:
(b) supplying a second bit-stream for the FPGA, wherein the second bit-stream is adapted to configure the FPGA to detect defects, and wherein the first bit-stream is adapted to be loaded into the FPGA in response to a detection of a defect by the FPGA when the FPGA is configured by the second bit-stream.
20 . The method of claim 19 , wherein the supplying of (a) and the supplying of (b) occur by supplying the device, and wherein the first and second bit-streams are stored in a memory in the device.
21 . The method of claim 18 , wherein the FPGA comprises a reflow control circuit, and wherein the power dissipation is increased by the reflow control circuit.
22 . The method of claim 18 , further comprising:
(c) detecting a temperature, wherein the power dissipation is increased based on the detecting of the temperature.
23 . The method of claim 22 , wherein the power dissipation of the plurality of logic gates is increased such that the temperature of the FPGA is increased greater than 0.5 degrees Centigrade per second.
24 . The method of claim 18 , wherein after the power dissipation is increased and the temperature of the device is increased, the temperature of the device is reduced such that the plurality of bond balls solidify.
25 . The method of claim 19 , further comprising:
(c) operating the FPGA after the plurality of bond balls solidify and after the FPGA is configured by the second bit-stream.
26 . The method of claim 18 , wherein the power dissipation is increased by increasing a clock rate.
27 . The method of claim 18 , wherein the plurality of bond balls comprise indium.
28 . The method of claim 18 , wherein the plurality of bond balls couples a semiconductor substrate to a circuit board, wherein a plurality of bond bumps couples the semiconductor substrate to the FPGA, and wherein the circuit board and the semiconductor substrate have disparate coefficients of linear thermal expansion.
29 . A method comprising:
(a) operating a device comprising a Field Programmable Gate Array (FPGA), a semiconductor substrate, a circuit board, a plurality of bond bumps and a plurality of bond balls, wherein the bond bumps are disposed between the FPGA and the semiconductor substrate, wherein the bond balls are disposed between the semiconductor substrate and the circuit board, wherein the FPGA includes logic gates, and wherein the device is operated such that the logic gates have a power dissipation that maintains a temperature of the device such that the bond balls remain solid; and
(b) supplying a bit-stream for the FPGA that configures the FPGA to increase the power dissipation of the logic gates such that the temperature of the device is increased and melts the bond balls.
30 . The method of claim 29 , wherein the bit-stream configures a reflow control circuit in the FPGA, and wherein the increasing the power dissipation is performed by the reflow control circuit.
31 . The method of claim 29 , further comprising:
(c) detecting a temperature, wherein the power dissipation is increased based on the detecting of the temperature.
32 . The method of claim 29 , wherein the power dissipation of the logic gates is increased such that the temperature of the device is increased greater than 0.5 degrees Centigrade per second.
33 . The method of claim 29 , wherein after the power dissipation is increased and the temperature of the device is increased, the temperature of the device is reduced such that the bond balls solidify.
34 . The method of claim 29 , further comprising:
(c) operating the device after the bond balls solidify and after the FPGA is configured by the bit-stream.
35 . The method of claim 29 , wherein the power dissipation is increased by increasing a clock rate.
36 . The method of claim 29 , wherein the bond balls comprise indium.
37 . The method of claim 29 , wherein the circuit board and the semiconductor substrate have disparate coefficients of linear thermal expansion.