Phase-locked loop apparatus and method

1. A low-power fractional-N phase-locked loop (PLL), comprising:

an oscillator with an output, the oscillator capable of oscillating at a first frequency, where the first frequency is controllable by at least a first control parameter;

a time-to-digital converter (TDC) with a first input coupled to a reference clock input of the PLL, a second input directly coupled to the oscillator output, and an output register capable of holding a measured phase value, the TDC comprising a fine TDC with an input coupled with the second TDC input, the fine TDC being configured for measuring a fractional component of a phase of an oscillator signal at the second TDC input; and

a system configured for comparing the measured phase value with a desired phase value to obtain a phase error signal, and for filtering the phase error to obtain a first control parameter signal for the oscillator.

2. The PLL of claim 1 , wherein the TDC further comprises:

a modulus-K counter coupled with the second TDC input, the modulus-K counter configured for measuring an integer component of the phase of the oscillator signal at the second TDC input, and a K-value of the modulus-K counter being at least twice a maximum number of oscillator cycles expected during a cycle of a reference clock input signal.

3. The PLL of claim 1 , wherein the TDC further comprises:

a modulus-K counter coupled with the second TDC input, the modulus-K counter configured for measuring an integer component of the phase of the oscillator signal at the second TDC input, and a K-value of the modulus-K counter being a power of two.

4. The PLL of claim 3 , wherein the system includes:

a first modulus-K summer with a first input for receiving an N-value, the N-value specifying an integer part of a desired frequency multiplication factor, and a second input; and

a first register with a first input coupled with an output of the first modulus-K summer, a second input coupled with the PLL reference clock input, and an output coupled with the second input of the first modulus-K summer, wherein the output of the first register is configured to provide at least a partial prediction of a phase.

5. The PLL of claim 4 , wherein the system includes:

a second modulus-K summer with a first input for receiving an M-value, the M-value specifying a fractional part of the desired frequency multiplication factor, an overflow output coupled with a third input of the first modulus-K summer, and a second input;

a second register with a first input coupled with a second output of the second modulus-K summer, a second input coupled with the PLL reference clock input, an output coupled with the second input of the second modulus-K summer;

a scaler with an input coupled to the output of the first register;

a third summer with a first input coupled with an output of the scaler and a second input coupled with the output of the second register, wherein an output of the third summer is configured to provide at least a partial prediction of a phase.

6. The PLL of claim 5 , wherein the M-value specifies a fractional part of the desired frequency multiplication factor at a resolution that matches a resolution of the fine TDC, the PLL further comprising an interpolator including:

an input for receiving a sub-M-value, the sub-M-value specifying an even smaller fractional part of the desired frequency multiplication factor; and

an output coupled with a third input of the second modulus-K summer;

wherein:

the interpolator is configured to output a number that, averaged over time, is smaller than 1 and represents the sub-M-value.

7. The PLL of claim 3 , wherein the TDC further comprises:

a sampler with a first input coupled with an output of the modulus-K counter and a second input coupled with the first TDC input, the sampler comprising a register clocked by an active edge of a reference clock signal, wherein the register will store an output value of the modulus-K counter upon receiving the active edge of the reference clock signal.

8. The PLL of claim 7 , wherein the TDC further comprises:

a scaler coupled with an output of the sampler; and

a summer with a first input coupled with an output of the scaler and a second input coupled with an output of the fine TDC.

9. The PLL of claim 7 , wherein the TDC further comprises:

a synchronization block configured to provide inputs to the sampler and to the fine TDC to align a fine TDC initial count with a change of the sampler register.

10. The PLL of claim 1 , wherein the system comprises a digital processor coupled with the TDC, the oscillator, and a processor-readable storage device, wherein the processor-readable storage device includes one or more instructions executable by the digital processor to perform the following acts:

calculating a desired phase by integrating a parameter indicating a desired frequency multiplication factor; and

comparing the desired phase with the measured phase value to calculate the phase error signal.

11. The PLL of claim 1 , wherein the system comprises a digital processor coupled with the TDC, the oscillator, and a processor-readable storage device, wherein the processor-readable storage device includes one or more instructions executable by the digital processor to perform the following act:

filtering the phase error signal.

12. The PLL of claim 1 , wherein the system comprises a digital-to-analog converter followed by an analog loop filter, or a digital loop filter followed by a digital-to-analog converter.

13. The PLL of claim 1 , wherein the TDC comprises:

a pulse hider coupled between the second TDC input and the input of the fine TDC, wherein:

the pulse hider is configured to only forward the oscillator signal from the second TDC input to the fine TDC near the time that an active edge is expected from a reference clock input signal at the first TDC input.

14. A method for fast locking a phase of an oscillator output signal to a phase of a reference clock signal comprising:

operating an oscillator having an output signal with a first frequency, where the first frequency is controllable by at least a first control parameter;

receiving a first active edge of the reference clock signal;

upon receiving the first active edge, starting to count a number of cycles of the oscillator output signal;

upon receiving the first active edge, setting a value of a phase prediction parameter to a first value;

receiving a second active edge of the reference clock signal;

upon receiving the second active edge, determining a first phase of the oscillator output signal, wherein the first phase includes an accumulated count of the number of cycles of the oscillator output signal;

upon receiving the second active edge, increasing the value of the phase prediction parameter with a desired frequency multiplication factor value;

subtracting the first phase of the oscillator output signal from the value of the phase prediction parameter to obtain a phase error value;

determining a rate of change of the phase error value;

filtering the phase error value with a first set of loop filter parameters;

filtering the rate of change with a second set of loop filter parameters;

combining or selecting between the results of low-pass filtering the phase error and low-pass filtering the rate of change to determine a new value of the first control parameter; and

forwarding the new value of the first control parameter to the oscillator to obtain a fast lock of the oscillator output signal phase to the phase of the reference clock signal.

15. The method of claim 14 , further comprising:

determining if the rate of change of the phase error value is low; and

in response to determining that the rate of change of the phase error is low, setting a lock detect flag.