Liquid crystal display device

Inventor: Atsushi Umezaki (Kanagawa, JP)

Assignee: Semiconductor Energy Laboratory Co., Ltd.

H01L27/124 G09G3/342 G09G3/3674 G09G3/3685 G11C19/28 H01L27/06 H01L27/1225 H01L27/1255 H01L27/15 G02F1/1393 G02F1/133753 G02F2001/133622 G09G3/3655 G09G2310/024 G09G2320/0252

View Patent ↗

Loading inventors, assignments & file history…

Monitor This Case

Get email alerts when status or documents change.

Order Certified Copies

Most orders are placed with the USPTO same day — all within 24 business hours.

Order via The Patent Place →

Pre-filled with this patent's details

Quick Facts

Patent No.: US 9,184,183
App. No.: 14/168,058
Granted: Nov 10, 2015
Kind: B2

External Links

USPTO Patent Center↗ Full Patent PDF↗

Abstract

A first transistor, a second transistor, a third transistor, a fourth transistor are provided. In the first transistor, a first terminal is electrically connected to a first wiring; a second terminal is electrically connected to a gate terminal of the second transistor; a gate terminal is electrically connected to a fifth wiring. In the second transistor, a first terminal is electrically connected to a third wiring; a second terminal is electrically connected to a sixth wiring. In the third transistor, a first terminal is electrically connected to a second wiring; a second terminal is electrically connected to the gate terminal of the second transistor; a gate terminal is electrically connected to a fourth wiring. In the fourth transistor, a first terminal is electrically connected to the second wiring; a second terminal is electrically connected to the sixth wiring; a gate terminal is connected to the fourth wiring.

Claims (73)

1. A semiconductor device comprising:

first to fifth transistors; and

first to sixth wirings,

wherein one of a source and a drain of the first transistor is electrically connected to the first wiring,

wherein the other of the source and the drain of the first transistor is electrically connected to the second wiring,

wherein one of a source and a drain of the second transistor is electrically connected to the third wiring,

wherein the other of the source and the drain of the second transistor is electrically connected to the second wiring,

wherein a gate of the second transistor is electrically connected to the fourth wiring,

wherein one of a source and a drain of the third transistor is electrically connected to the fifth wiring,

wherein the other of the source and the drain of the third transistor is electrically connected to a gate of the first transistor,

wherein a gate of the third transistor is electrically connected to the fifth wiring,

wherein one of a source and a drain of the fourth transistor is electrically connected to the third wiring,

wherein the other of the source and the drain of the fourth transistor is electrically connected to the gate of the first transistor,

wherein a gate of the fourth transistor is electrically connected to the fourth wiring,

wherein one of a source and a drain of the fifth transistor is electrically connected to the third wiring,

wherein the other of the source and the drain of the fifth transistor is electrically connected to the second wiring, and

wherein a gate of the fifth transistor is electrically connected to the sixth wiring.

2. The semiconductor device according to claim 1 , further comprising a capacitor,

wherein one electrode of the capacitor is electrically connected to the gate of the first transistor, and

wherein the other electrode of the capacitor is electrically connected to the other of the source and the drain of the first transistor.

3. A display module comprising the semiconductor device according to claim 1 .

4. An electronic appliance comprising the display module according to claim 3 .

5. A semiconductor device comprising:

first to fifth transistors; and

first to sixth wirings,

wherein at least one of the first to fifth transistors comprises a channel formation region that includes an oxide semiconductor,