IP Library Granted Patent US 8,946,769
Granted Patent B2
US 8,946,769 · App. 14/168,300 · Granted Feb 3, 2015

Lateral devices containing permanent charge

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Quick Facts
Patent No.
US 8,946,769
App. No.
14/168,300
Granted
Feb 3, 2015
Kind
B2
Abstract

A lateral device includes a gate region connected to a drain region by a drift layer. An insulation region adjoins the drift layer between the gate region and the drain region. Permanent charges are embedded in the insulation region, sufficient to cause inversion in the insulation region.

Claims (32)

1. A lateral semiconductor device comprising:

a first-conductivity-type source region;

a second-conductivity-type body region interposed between said source region and a semiconductor drift region;

said drift region being laterally interposed between said body region and a first-conductivity-type drain region; and

permanent charge, embedded in at least one insulating region which vertically adjoins said drift region, which has a polarity which tends to deplete a layer of said drift region in proximity to said insulating region.

2. The lateral semiconductor device of claim 1 , wherein said drift region is formed as a well.

3. The lateral semiconductor device of claim 1 , further comprising a buried region within said drift region.

4. The lateral semiconductor device of claim 1 , further comprising a trench gate.

5. The lateral semiconductor device of claim 4 , wherein said trench gate is between said source region and said drain region.

6. The lateral semiconductor device of claim 4 , wherein said trench gate extends laterally into said insulating region.

7. The lateral semiconductor device of claim 4 , further comprising a second buried region.

8. A lateral semiconductor device, comprising:

a second-conductivity-type body region interposed between a first-conductivity-type source region and a drift region, said drift region being laterally interposed between said body region and a first-conductivity-type drain region;

a surface region within said drift region; and

permanent charge, embedded in at least one insulating region which vertically adjoins said drift region, which has a polarity which tends to invert said surface region in proximity to said insulating region.

9. The lateral semiconductor device of claim 8 , wherein said drift region is formed as a well.

10. The lateral semiconductor device of claim 8 , further comprising a buried region within said drift region.

11. The lateral semiconductor device of claim 8 , further comprising a trench gate.

12. The lateral semiconductor device of claim 11 , wherein said trench gate is interposed between said source region and said drain region.

13. The lateral semiconductor device of claim 11 , wherein said trench gate extends laterally above said surface region.

14. The lateral semiconductor device of claim 8 , wherein said surface region is adjacent to said body region.

15. The lateral semiconductor device of claim 8 , wherein said surface region is adjacent to said drain region.

16. A lateral semiconductor device, comprising:

a second-conductivity-type body region interposed between a first-conductivity-type source region and a drift region, said drift region being laterally interposed between said body region and a first-conductivity-type drain region;

a surface region within said drift region;

permanent charge, embedded in an insulation region which vertically adjoins said surface region, which has a polarity which tends to invert adjacent portions of said surface region; and

a trench gate;

wherein said source region is laterally interposed between said trench gate and said drain region.

17. The lateral semiconductor device of claim 16 , wherein said drift region is formed as a well.

18. The lateral semiconductor device of claim 16 , wherein said surface region is adjacent to said body region.

19. The lateral semiconductor device of claim 16 , wherein said surface region is adjacent to said drain region.

20. The lateral semiconductor device of claim 16 , further comprising a buried region within said drift region.

Assignments (1)
SECURITY INTEREST Recorded Dec 27, 2022
From: MAXPOWER SEMICONDUCTOR, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 062228/0648 →