Solid-state imaging device, manufacturing method thereof, and electronic apparatus
Disclosed herein is a solid-state imaging device including: a laminated semiconductor chip configured to be obtained by bonding two or more semiconductor chip sections to each other and be obtained by bonding at least a first semiconductor chip section in which a pixel array and a multilayer wiring layer are formed and a second semiconductor chip section in which a logic circuit and a multilayer wiring layer are formed to each other in such a manner that the multilayer wiring layers are opposed to each other and are electrically connected to each other; and a light blocking layer configured to be formed by an electrically-conductive film of the same layer as a layer of a connected interconnect of one or both of the first and second semiconductor chip sections near bonding between the first and second semiconductor chip sections. The solid-state imaging device is a back-illuminated solid-state imaging device.
1. A solid-state imaging device comprising:
a first semiconductor chip including a pixel array and a first multilayer wiring layer having a first connecting interconnect, and a second semiconductor chip including a logic circuit and a second multilayer wiring layer having a second connecting interconnect, wherein the first semiconductor chip and the second semiconductor chip are configured such that the first multilayer wiring layer and the second multilayer wiring layer are opposed to one another and are electrically connected to one another; and
a light blocking layer including a first electrically-conductive film of the same layer as one of the first connecting interconnect and the second connecting interconnect formed uniformly across a whole surface between the first semiconductor chip and the second semiconductor chip corresponding to the logic circuit,
wherein the solid-state imaging device is configured as a back-illuminated solid-state imaging device.
2. The solid-state imaging device according to claim 1 , wherein the light blocking layer further comprises a second electrically-conductive film of the same layer as the other of the first connecting interconnect and the second connecting interconnect.
3. The solid-state imaging device according to claim 1 , wherein the first multilayer wiring layer further comprises a first nonconnecting interconnect, wherein the first nonconnecting interconnect overlaps with the light blocking layer.
4. The solid-state imaging device according to claim 3 , wherein the first multilayer wiring layer further comprises an electrically-conductive via between the first connecting interconnect and the first nonconnecting interconnect.
5. The solid-state imaging device according to claim 1 , wherein the first connecting interconnect and the second connecting interconnect are directly bonded to one another at a bonding portion.
6. The solid-state imaging device according to claim 1 , wherein a material of the light blocking layer is selected from the group including Cu, Al, W, Ti, Ta, Mo, Ru, and alloys thereof.
7. The solid-state imaging device according to claim 1 , wherein a film thickness of the light blocking layer is between 50 and 800 nm.
8. A method of manufacturing a solid-state imaging device, the method comprising:
providing a first semiconductor chip including a pixel array and a first multilayer wiring layer having a first connecting interconnect;
providing a second semiconductor chip including a logic circuit and a second multilayer wiring layer having a second connecting interconnect;
forming a light blocking layer including a first electrically-conductive film of the same layer as one of the first connecting interconnect and the second connecting interconnect uniformly across a whole surface between the first semiconductor chip and the second semiconductor chip corresponding to the logic circuit; and
arranging the first semiconductor chip and the second semiconductor chip such that the first wiring layer and the second multilayer wiring layer are opposed to one another and are electrically connected to one another,
wherein the solid-state imaging device is configured as a back-illuminated solid-state imaging device.
9. The method of manufacturing a solid-state imaging device according to claim 8 , wherein the light blocking layer further comprises a second electrically-conductive film of the same layer as the other of the first connecting interconnect and the second connecting interconnect.
10. The method of manufacturing a solid-state imaging device according to claim 8 , wherein the first multilayer wiring layer further comprises a first nonconnecting interconnect, wherein the first nonconnecting interconnect overlaps with the light blocking layer.
11. The method of manufacturing a solid-state imaging device according to claim 10 , wherein the first multilayer wiring layer further comprises an electrically-conductive via between the first connecting interconnect and the first nonconnecting interconnect.
12. The method of manufacturing a solid-state imaging device according to claim 8 , further comprising:
directly bonding the first connecting interconnect and the second connecting interconnect to one another at a bonding portion.
13. An electronic apparatus comprising:
a solid-state imaging device;
an optical system configured to guide incident light to a photoelectric converter of the solid-state imaging device; and
a signal processing circuit configured to process an output signal of the solid-state imaging device,
wherein the solid state imaging device includes:
a first semiconductor chip including a pixel array and a first multilayer wiring layer having a first connecting interconnect, and a second semiconductor chip including a logic circuit and a second multilayer wiring layer having a second connecting interconnect, wherein the first semiconductor chip and the second semiconductor chip are configured such that the first multilayer wiring layer and the second multilayer wiring layer are opposed to one another and are electrically connected to one another; and
a light blocking layer including a first electrically-conductive film of the same layer as one of the first connecting interconnect and the second connecting interconnect formed uniformly across a whole surface between the first semiconductor chip and the second semiconductor chip corresponding to the logic circuit,
wherein the solid-state imaging device is configured as a back-illuminated solid-state imaging device.
14. The electronic apparatus according to claim 13 , wherein the light blocking layer further comprises a second electrically-conductive film of the same layer as the other of the first connecting interconnect and the second connecting interconnect.
15. The electronic apparatus according to claim 13 , wherein the first multilayer wiring layer further comprises a first nonconnecting interconnect, wherein the first nonconnecting interconnect overlaps with the light blocking layer.
16. The electronic apparatus according to claim 15 , wherein the first multilayer wiring layer further comprises an electrically-conductive via between the first connecting interconnect and the first nonconnecting interconnect.
17. The electronic apparatus according to claim 13 , wherein the first connecting interconnect and the second connecting interconnect are directly bonded to one another at a bonding portion.
18. The electronic apparatus according to claim 13 , wherein a material of the light blocking layer is selected from the group including Cu, Al, W, Ti, Ta, Mo, Ru, and alloys thereof.
19. The electronic apparatus according to claim 13 , wherein a film thickness of the light blocking layer is between 50 and 800 nm.