Wafer structure and power device using the same
View Patent ↗In one embodiment, a method of making a super-junction MOS transistor in a wafer can include: (i) forming a first doping layer having a high doping concentration; (ii) forming a second doping layer on the first doping layer, wherein a doping concentration of the second doping layer is less than a doping concentration of the first doping layer; (iii) forming a third doping layer on the second doping layer, wherein the third doping layer comprises an intrinsic layer; (iv) etching through the third doping layer and partially through the second doping layer to form trenches; and (v) filling the trenches to form pillar structures.
1. A wafer structure for a power device, the wafer structure comprising:
a) a first doping layer having a high doping concentration;
b) a second doping layer on said first doping layer, wherein a doping concentration of said second doping layer is less than said high doping concentration;
c) a third doping layer on said second doping layer, wherein a doping concentration of said third doping layer is less than said doping concentration of said second doping layer; and
d) pillar structures extending through said third doping layer and partially through said second doping layer, wherein each of said pillar structures comprises a bowl structure extending an entire thickness of said third doping layer.
2. The wafer structure of claim 1 , wherein said third doping layer comprises an intrinsic layer.
3. The wafer structure of claim 1 , wherein said doping concentration of said second doping layer is uniformly distributed.
4. The wafer structure of claim 1 , wherein said doping concentration of said second doping layer is gradiently distributed.
5. The wafer structure of claim 1 , wherein a type of impurity of said second doping layer is the same as a type of impurity of said first doping layer.
6. The wafer structure of claim 1 , wherein a type of impurity of said second doping layer is different than a type of impurity of said first doping layer.
7. The wafer structure of claim 1 , wherein said second and third doping layers are formed by epitaxial growth on said first doping layer.
8. A switching voltage regulator, comprising:
a) said wafer structure of claim 1 ; and
b) said power device formed in said wafer structure.
9. The switching voltage regulator of claim 8 , wherein said power device comprises a metal oxide semiconductor field-effect transistor (MOSFET).
10. The switching voltage regulator of claim 9 , wherein said MOSFET comprises a longitude super-junction metal oxide field-effect transistor or a vertical double diffused metal oxide semiconductor field-effect transistor.
11. The switching voltage regulator of claim 10 , wherein said longitude super-junction metal oxide field-effect transistor is manufactured by a trench fill process.
12. The switching voltage regulator of claim 9 , wherein said MOSFET comprises a vertical double diffused metal oxide semiconductor field-effect transistor.
13. The switching voltage regulator of claim 8 , wherein said power device comprises an insulated gate bipolar transistor (IGBT).
14. The switching voltage regulator of claim 8 , wherein said power device comprises a diode.
15. A method of making a super-junction MOS transistor in a wafer, the method comprising:
a) forming a first doping layer having a high doping concentration;
b) forming a second doping layer on said first doping layer, wherein a doping concentration of said second doping layer is less than a doping concentration of said first doping layer;
c) forming a third doping layer on said second doping layer, wherein said third doping layer comprises an intrinsic layer;
d) etching through said third doping layer and partially through said second doping layer to form trenches; and
e) filling said trenches to form pillar structures, wherein each of said pillar structures comprises a bowl structure extending an entire thickness of said third doping layer.
16. The method of claim 15 , wherein said forming said first doping layer comprises heavily doping a silicon substrate with n-type impurities.
17. The method of claim 15 , wherein said forming said second doping layer comprises lightly doping said second doping layer with n-type impurities.
18. The method of claim 15 , wherein said filling said trenches comprises using silicon material with p-type impurities therein.
19. The method of claim 15 , wherein said bowl structure in said third doping layer is configured to extend a terminal surface for a super-junction MOS transistor.
20. The method of claim 15 , further comprising:
a) forming a field oxide on a surface of said pillar structures and said third doping layer; and
b) depositing a metal layer at least partially on said field oxide.