Thickened sidewall dielectric for memory cell
Methods and devices are disclosed, such as those involving memory cell devices with improved charge retention characteristics. In one or more embodiments, a memory cell is provided having an active area defined by sidewalls of neighboring trenches. A layer of dielectric material is blanket deposited over the memory cell, and etched to form spacers on sidewalls of the active area. Dielectric material is formed over the active area, a charge trapping structure is formed over the dielectric material over the active area, and a control gate is formed over the charge trapping structure. In some embodiments, the charge trapping structure includes nanodots. In some embodiments, the width of the spacers is between about 130% and about 170% of the thickness of the dielectric material separating the charge trapping material and an upper surface of the active area.
1. A memory device, comprising:
a semiconductor material;
an oxide material on an uppermost surface of the semiconductor material;
a recess extending through the oxide material and partially through the semiconductor material, the recess bounded by a pair of spacers that are separated from each other by a space within the recess, wherein the spacers comprise a dielectric material that contacts sidewalls of the oxide material and the semiconductor material along sidewalls of the recess;
a first dielectric material within the recess and contacting the semiconductor material along a bottom of the recess, the first dielectric material having an upper surface elevationally below the uppermost surface of the semiconductor material;
a charge trapping structure over the upper surface of the first dielectric material and extending laterally outward from the recess over the oxide material;
a second dielectric material on the charge trapping structure; and
a conductor material on the second dielectric material and extending within the recess.
2. The memory device of claim 1 , wherein the charge trapping structure comprises a plurality of nanodots.
3. The memory device of claim 2 , wherein the nanodots comprise metallic nanodots.
4. The memory device of claim 3 wherein the metallic nanodots are formed of a metallic material selected from the group consisting of Pt, Ru, W and WN.
5. The memory device of claim 1 , wherein the conductor material forms a control gate configured to be biased such that electrons are caused to tunnel between the semiconductor material and the charge trapping structure.
6. The memory device of claim 1 , wherein the spacers comprise silicon nitride.
7. The memory device of claim 6 , wherein the first dielectric comprises silicon oxide.
8. The memory device of claim 1 , wherein the conductor material comprises a material selected from the group consisting of Si, WSi x , TaSi x , and NiSi x .
9. The memory device of claim 1 , wherein a width of the recess is between about 300 Å and about 450 Å when measured at an opposite end of the recess.
10. The memory device of claim 1 wherein the thickness of the spacers exceeds about 100 Å.
11. The memory device of claim 1 , wherein the charge trapping structure extends to cover sidewalls of the spacers in the recess.
12. The memory device of claim 1 , wherein the second dielectric material extends to cover sidewalls of the spacers in the recess.
13. A memory device, comprising:
a semiconductor material;
an oxide material over an uppermost surface of the semiconductor material;
an opening extending through the oxide material and partially through the semiconductor material;
a first dielectric material within the opening on the semiconductor material, the first dielectric material having an upper surface;
a charge trapping structure on the first dielectric material;
a second dielectric material on the charge trapping material; and
a pair of spacers within the opening, the pair of spacers being in direct contact with sidewalls of the oxide material and sidewalls of the semiconductor material and being separated from each other by a gap having a base corresponding to a portion of the upper surface of the first dielectric material between the spacers, the charge trapping structure and the second dielectric material extending within the opening and across the base and extending laterally outward from the opening over the oxide material;
a conductor material on the second dielectric material.