Memory system having high data transfer efficiency and host controller

1. A host system comprising:

a CPU;

a host controller;

a system memory configured to be accessed by the CPU and the host controller; and

a memory device which is connected to the host controller through an interface,

wherein the CPU is configured to execute a host driver to control the host controller,

each of first, third, and fourth descriptors has an attribute field for identifying a type of the descriptors, and designating a processing method of the descriptors,

wherein the host controller includes:

a register set which is configured to store a part of information in the third descriptor;

a command controller which is configured to issue a command to the memory device according to the information stored in the register set; and

a direct memory access (DMA) unit which is configured to load the first, third, and fourth descriptors into the host controller, and is configured to transfer data between the system memory and the memory device according to the first, third, and fourth descriptors,

the first descriptor includes a plurality of pointers with attributes,

each of the pointers of the first descriptor indicates a leading region of the third descriptor,

the third descriptor includes command issue information and attributes,

the fourth descriptor includes a number of DMA execution information and attributes,

wherein the DMA unit is configured (1) to load the first descriptor, (2) to acquire the pointer from the loaded first descriptor, (3) to load the third descriptor and the fourth descriptor based on the acquired pointer, (4) to execute a data transfer between the system memory and the memory device, (5) to repeat the process of (2) to (4) until the attribute of the first descriptor indicates the end of descriptor, and (6) to generate an interrupt to the CPU when the data transfer is end or during a DMA data transfer, and

wherein the host driver is configured (1) to generate the first, third and fourth descriptors into the system memory according to an data read/write request of an application from/to the memory device, (2) to start the DMA unit when a location of the first descriptor is set to the host controller, and (3) to deal with the interrupts until the DMA unit indicates completion of the data transfer of the first descriptor.

2. The host system according to claim 1 , wherein the DMA unit comprises: a system address controller configured to control addresses of the system memory pointing data and each descriptor; and a data buffer configured to store data from the system memory and restore the data to write the data to the memory device, or to store data from the memory device and restore the data to write the data to the system memory.

3. The host system according to claim 1 , wherein the third descriptors includes information necessary to generate a data transfer command of the memory device; a command argument, a command number, a command operation mode, a block length, and the number of blocks; wherein the fourth descriptors includes information indicating necessary to designate system memory areas; addresses, and sizes for each a plurality of scattered data in the system memory.

4. The host system according to claim 1 , wherein the data transfer between the host controller and the memory device is started by a memory read/write command which is issued by command controller when setting of the register set is completed, and the memory device acquires information necessary for the data transfer from the command.