IP Library Granted Patent US 9,342,260
Granted Patent B2
US 9,342,260 · App. 14/175,553 · Granted May 17, 2016

Methods for writing data to non-volatile memory-based mass storage devices

Inventors: Franz Michael Schuette (Colorado Springs, CO); William Ward Clawson (Hollister, CA)
Assignee: OCZ Storage Solutions Inc.
G06F3/0679G06F3/064G06F3/0616G06F3/0619G06F3/0629G06F3/0688G11C16/349G06F12/0246G06F2212/7201
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Quick Facts
Patent No.
US 9,342,260
App. No.
14/175,553
Granted
May 17, 2016
Kind
B2
Abstract

Methods of operating a non-volatile solid state memory-based mass storage device having at least one non-volatile memory component. In one aspect of the invention, the one or more memory components define a memory space partitioned into user memory and over-provisioning pools based on a P/E cycle count stored in a block information record. The storage device transfers the P/E cycle count of erased blocks to a host and the host stores the P/E cycle count in a content addressable memory. During a host write to the storage device, the host issues a low P/E cycle count number as a primary address to the content addressable memory, which returns available block addresses of blocks within the over-provisioning pool as a first dimension in a multidimensional address space. Changed files are preferably updated in append mode and the previous version can be maintained for version control.

Claims (9)

1. In a computer system comprising a host, a method of storing data in a non-volatile solid state memory-based mass storage device, the mass storage device having a substrate and at least one non-volatile memory component mounted thereon, memory locations in the non-volatile memory component having first order addresses and second order addresses, the method comprising:

generating with the non-volatile memory component a record of the number of programming cycles relating to the first order address;

transmitting the record to the host;

selecting with the host a low number of programming cycles within a range of numbers of programming cycles of records relating to the first order addresses as an initial address for a write access to the non-volatile memory device.

2. The method of claim 1 , wherein the non-volatile memory components are NAND flash memory components and the first order addresses correspond to block addresses.

3. The method of claim 1 , wherein the host issues a low number of the range of numbers of programming cycles to a content addressable memory and the content addressable memory returns the addresses of available blocks.

4. The method of claim 3 , wherein the memory locations corresponding to the first order addresses in the non-volatile memory device comprise a user memory space and an over-provisioning memory space.

5. The method of claim 4 , wherein the number of programming cycles of the first order addresses only from blocks assigned to the over-provisioning pool is transmitted to the host.

6. The method of claim 5 wherein, after a block is completely written, it is moved into the user memory space.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 1, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043397/0380 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 14, 2016
From: OCZ STORAGE SOLUTIONS, INC.
To: TOSHIBA CORPORATION
Reel/Frame 038434/0371 →
Continuity (3)
Division 13251491 · Oct 3, 2011
Provisional Application 61532680 · Sep 9, 2011
Related Publication 20140156921A1 · Jun 5, 2014