Method of forming a CMOS structure having gate insulation films of different thicknesses
View Patent ↗The semiconductor integrated circuit device employs on the same silicon substrate a plurality of kinds of MOS transistors with different magnitudes of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of the two power supply units.
1. A method of manufacturing a semiconductor integrated circuit device comprising:
forming a first MOS transistor having a gate insulation film of a first thickness;
forming a second MOS transistor having a insulative film with a second thickness that is greater than the first thickness of the gate insulation film of said first MOS transistor,
wherein said first MOS transistor is configured for use with a logic circuit required to exhibit enhanced switching speed whereas said second transistor is configured for use with a circuit with less switching speed than said logic circuit while allowing a power supply of said first MOS transistor to be controlled independently of a power supply of said second MOS transistor.
2. A method of manufacturing a semiconductor integrated circuit device comprising:
forming a first MOS transistor having a first gate electrode, a first electrode and a second electrode, and
forming a second MOS transistor with a second gate elect rode, a third electrode and a fourth electrode, wherein said first electrode is connected to a first potential, said second electrode is connected to said third electrode, and said fourth electrode is connected to a second potential, and wherein said first MOS transistor has a gate insulation film thickness that is less than the thickness of said second MOS transistor.
3. The method of manufacturing a semiconductor integrated circuit device according to claim 1 , wherein said first MOS transistor has as gate length that is less than said second MOS transistor.
4. The method of manufacturing a—semiconductor integrated circuit device according to claim 1 , wherein said first MOS transistor has a gate voltage that is less than said second MOS transistor.
5. A method of manufacturing a semiconductor integrated circuit device comprising:
forming a first MOS transistor;
forming a second MOS transistor having the same conductivity type as the first MOS transistor and providing a gate insulation film thickness that is thicker than the first MOS transistor and a drain connected to the first MOS transistor; and
connecting a power supply line to a source of the second MOS transistor, wherein a control signal having a first state for allowing the second MOS transistor to be in an on-state and a second state for allowing the second MOS transistor to be in an off-state is applied to a gate of the second MOS transistor.
6. The method of manufacturing a semiconductor integrated circuit device according claim 5 , wherein a gate insulation film thickness of the first MOS transistor is 3.5 nm or less.
7. The method of manufacturing a semiconductor integrated circuit device according to claim 6 , wherein a gate insulation film thickness of the second MOS transistor is 5.0 nm or more.
8. The method of manufacturing a semiconductor integrated circuit device according to claim 7 , wherein a gate insulation film thickness of the second MOS transistor is 10.0 nm or more.
9. The method of manufacturing a semiconductor integrated circuit device according to claim 6 , wherein a gate length of the second MOS transistor is longer than that of the first MOS transistor.
10. The method of manufacturing a semiconductor integrated circuit device according to claim 6 , further comprising:
forming a third MOS transistor having a drain connected to a drain of the first MOS transistor and a gate insulation film thickness being thinner that that of the second MOS transistor; and
connecting another power supply line to a source of the third MOS transistor, wherein the first and the second MOS transistors provide N-channel type, respectively; and the third MOS transistor has a different conductivity type than the first and the second MOS transistors.
11. The method of manufacturing a semiconductor integrated circuit device according to claim 10 , wherein gates of the first and the third MOS transistors are short-circuited.
12. The method of manufacturing a semiconductor integrated circuit device according to claim 6 , wherein a gate insulation film thickness of the first MOS transistor is 3.0 nm or less.
13. The method of manufacturing a semiconductor integrated circuit device according to claim 12 , wherein a gate insulation film thickness of the first MOS transistor is 2.0 nm or less.
14. The method of manufacturing a semiconductor integrated circuit device according to claim 5 , wherein a gate insulation film thickness of the second MOS transistor is 5.0 nm or more.
15. The method of manufacturing a semiconductor integrated circuit device according to claim 14 , wherein a gate insulation film thickness of the second MOS transistor is 10.0 nm or more.
16. The method of manufacturing a semiconductor integrated circuit device according to claim 15 , wherein a length of the second MOS transistor is longer than that of the first MOS transistor.
17. The method of manufacturing a semiconductor integrated circuit device according to claim 15 , further comprising:
forming a third MOS transistor having a drain connected to a drain of the first MOS transistor and a gate insulation film thickness being thinner than the second MOS transistor;
forming another power supply line connected to a source of the third MOS transistor, wherein the first and the second MOS transistor provide N-channel type, respectively; and
forming a third MOS transistor has a different conductivity type with the first and the second MOS transistors.
18. The method of manufacturing a semiconductor integrated circuit device according to claim 5 , wherein gates of the first and the third MOS transistor are short-circuited.
19. The method of manufacturing a semiconductor integrated circuit device according to claim 5 , wherein an amplitude of voltage applied to the gate of the first MOS transistor is smaller than that of voltage applied to the gate of the second MOS transistor.
20. A method of manufacturing a semiconductor integrated circuit device comprising:
forming a first MOS transistor;
forming a second MOS transistor having the same conductivity type as the first MOS transistor and a drain connected to a source of the first MOS transistor;
connecting a power supply line to the source of the second MOS transistor, wherein a control signal having a first state for allowing the second MOS transistor to be in an on-state and a second state for allowing the second MOS transistor to be in an off-sate is applied to the gate of second MOS transistor; and
generating a tunnel current between the gate and the source of the first MOS transistor that is smaller than a tunnel current generated between the gate and the source of the first MOS transistor when a voltage difference between the respective sources of the first and the second MOS transistors is identical.